{"id":{"repo_id":"regina","oai_identifier":"oai:uregina.scholaris.ca:10294/12682"},"canonical_url":"https://search.dev.ndltd.org/etd/regina/oai:uregina.scholaris.ca:10294/12682","repository":{"repo_id":"regina","name":"University of Regina","base_url":"https://uregina.scholaris.ca/server/oai/request"},"display":{"title":"JTSim: A simulator for thread scheduling.","abstract":"","abstract_html":null,"abstract_has_math":false,"creators":["Thomas, Michael C."],"institution":"Faculty of Graduate Studies and Research, University of Regina","degree_name":"Master of Science (MSc)","degree_level":"Master&apos;s","degree_discipline":"Computer science","degree_department":null,"school":null,"contributors":[],"advisors":["Hamilton, Howard J."],"committee_chairs":[],"committee_members":[],"year":1998,"date_issued":"1998","date_published":"1998","updated_at":"2026-07-24T04:03:30Z","subjects":[],"languages":["EN"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier.doi","label":"DOI","values":["https://doi.org/10.82465/3994"],"render_values":[{"text":"https://doi.org/10.82465/3994","href":"https://doi.org/10.82465/3994","code":true}]}]},"links":{"outbound_url":"https://hdl.handle.net/10294/12682","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Hamilton, Howard J."]},{"key":"dc:creator","label":"Author","values":["Thomas, Michael C."]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2021-09-21T12:41:21Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2021-09-21T12:41:21Z"]},{"key":"dc:date.issued","label":"Date","values":["1998"]},{"key":"dc:publisher","label":"Institution","values":["Faculty of Graduate Studies and Research, University of Regina"]},{"key":"dc:type","label":"Dc Type","values":["master thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Master&apos;s"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science (MSc)"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["EN"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.doi","label":"DOI","values":["https://doi.org/10.82465/3994"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://hdl.handle.net/10294/12682"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:title","label":"Title","values":["JTSim: A simulator for thread scheduling."]}]}],"canonical_facts":{"dc:contributor.advisor":["Hamilton, Howard J."],"dc:creator":["Thomas, Michael C."],"dc:date.accessioned":["2021-09-21T12:41:21Z"],"dc:date.available":["2021-09-21T12:41:21Z"],"dc:date.issued":["1998"],"dc:identifier.doi":["https://doi.org/10.82465/3994"],"dc:identifier.uri":["https://hdl.handle.net/10294/12682"],"dc:language.iso":["EN"],"dc:publisher":["Faculty of Graduate Studies and Research, University of Regina"],"dc:title":["JTSim: A simulator for thread scheduling."],"dc:type":["master thesis"],"thesis:degree_discipline":["Computer science"],"thesis:degree_level":["Master&apos;s"],"thesis:degree_name":["Master of Science (MSc)"]},"updated_at":"2026-07-24T04:03:30Z"}