Efficiency improvement in nanometre CMOS outphasing power amplifiers
There is a pressing need for high-efficiency linear power amplifiers (PA) due to consumer demand for greater mobile data rates and battery lifetimes. The outphasing transmitter is one such technique that warrants research as it has yet to achieve commercial viability. It operates by decomposing a modulated signal into two constant-amplitude signals with a phase difference corresponding to the normalised envelope amplitude, amplifying them with high-efficiency PAs, and then summing them to reconstruct the envelope. Silicon is a promising semiconductor for outphasing as the signal processing circuitry and PA can reside on the same die however silicon PAs suffer from low output power due to the sub-1V supply voltages and lossy passive components. This thesis focuses on improving the design of CMOS outphasing PAs which utilise unisolated power combiners and switched-mode voltage-source PA stages. Power combiner design is advanced with the creation of two novel three-port coupled coils which allow multiple inductors to be merged into a single compact low-loss structure. Four Wilkinson power combiners were fabricated to demonstrate and evaluate the coupled coils with one combiner requiring only three components by harnessing resistive coil parasitics. The most popular voltage-source CMOS PA, the complementary Class-D, suffers from shoot-through current losses where the supply voltage is shorted to ground during switching. The short-circuit can be prevented by driving the two transistors with dead-time-separated voltages to stop them from switching simultaneously. To investigate this technique, a hard-switching CMOS PA with a novel driver that generates two dead-time-separated signals was designed, fabricated, and evaluated. A thorough analysis of the dead-time technique is presented, something hitherto absent in the literature. The third fabricated chip completes the work by pairing an unisolated coupled-coil power combiner with a switched-mode PA stage featuring an improved dead-time technique.
22 nm, cascode, CMOS, coupled coil, driver, impedance matching, integrated circuit, lumped element, mutual coupling, outphasing, power amplifier, power combiners, reactive compensation, shoot-through current, switched-mode, Wilkinson
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