Six-port wireless receiver architectures

This work describes novel six-port direct conversion digital receiver architecture.<br/><br/>A general review of six -port reflectometer theory and architectures is presented. Three six-port architectures suitable for MMIC realization are discussed. <br/><br/>A new broadband six-port direct conversion wireless receiver architecture is proposed, designed and characterised. This receiver can operate from 900 MHz to4 GHz and can give bit error rate as low as 8E-7 for input power levels of - 37 dBm without a low noise amplifier. In addition three robust novel methods for the calibration of the six-port digital receiver, which relate to dual-tone calibration. receiver frequency synchronization and dual-tone linearization of on­board diode detector are also proposed.<br/><br/>A modelling strategy for each of the lumped elements required to construct a six-port digital receiver using RFCMOS technology has been studied. Novel models and design rules for CMOS capacitor and inductor design have been given. The various methodologies for the design of a RF CMOS MMIC low noise amplifier are also discussed and a CMOS MMIC low noise amplifier is designed.<br/>

Name dc:type.qualificationname

Doctor of Philosophy

Level dc:type.qualificationlevel

Doctoral Thesis

Grantor dc:publisher.institution

Queen's University Belfast

Year dc:date.issued

2004

Author dc:creator

• Xiong, Xiang Zheng

Advisor dc:contributor.advisor

• Fusco, Vincent

Language dc:language

eng

Identifier

oai:pure.qub.ac.uk/portal:studenttheses/84c37800-9373-4ecc-9a35-61c747d19517

OAI identifier oai:identifier

oai:pure.qub.ac.uk/portal:studenttheses/84c37800-9373-4ecc-9a35-61c747d19517