{"id":{"repo_id":"purdue-thes","oai_identifier":"oai:docs.lib.purdue.edu:open_access_dissertations-2611"},"canonical_url":"https://search.dev.ndltd.org/etd/purdue-thes/oai:docs.lib.purdue.edu:open_access_dissertations-2611","repository":{"repo_id":"purdue-thes","name":"Purdue University","base_url":"https://docs.lib.purdue.edu/do/oai/"},"display":{"title":"FABRICATION AND CHARACTERIZATION OF ACTIVE NANOSTRUCTURES","abstract":"Three different nanostructure active devices have been designed, fabricated and characterized. Junctionless transistors based on highly-doped silicon nanowires fabricated using a bottom-up fabrication approach are first discussed. The fabrication avoids the ion implantation step since silicon nanowires are doped in-situ during growth. Germanium junctionless transistors fabricated with a top down approach starting from a germanium on insulator substrate and using a gate stack of high-k dielectrics and GeO2 are also presented. The levels and origin of low-frequency noise in junctionless transistor devices fabricated from silicon nanowires and also from GeOI devices are reported. Low-frequency noise is an indicator of the quality of the material, hence its characterization can reveal the quality and perhaps reliability of fabricated transistors. A novel method based on low-frequency noise measurement to envisage trap density in the semiconductor bandgap near the semiconductor/oxide interface of nanoscale silicon junctionless transistors (JLTs) is presented. Low-frequency noise characterization of JLTs biased in saturation is conducted at different gate biases. The noise spectrum indicates either a Lorentzian or 1/f. A simple analysis of the low-frequency noise data leads to the density of traps and their energy within the semiconductor bandgap. The level of noise in silicon JLT devices is lower than reported values on transistors fabricated using a top-down approach. This noise level can be significantly improved by improving the quality of dielectric and the channel interface.","abstract_html":"Three different nanostructure active devices have been designed, fabricated and characterized. Junctionless transistors based on highly-doped silicon nanowires fabricated using a bottom-up fabrication approach are first discussed. The fabrication avoids the ion implantation step since silicon nanowires are doped in-situ during growth. Germanium junctionless transistors fabricated with a top down approach starting from a germanium on insulator substrate and using a gate stack of high-k dielectrics and GeO2 are also presented. The levels and origin of low-frequency noise in junctionless transistor devices fabricated from silicon nanowires and also from GeOI devices are reported. Low-frequency noise is an indicator of the quality of the material, hence its characterization can reveal the quality and perhaps reliability of fabricated transistors. A novel method based on low-frequency noise measurement to envisage trap density in the semiconductor bandgap near the semiconductor/oxide interface of nanoscale silicon junctionless transistors (JLTs) is presented. Low-frequency noise characterization of JLTs biased in saturation is conducted at different gate biases. The noise spectrum indicates either a Lorentzian or 1/f. A simple analysis of the low-frequency noise data leads to the density of traps and their energy within the semiconductor bandgap. The level of noise in silicon JLT devices is lower than reported values on transistors fabricated using a top-down approach. This noise level can be significantly improved by improving the quality of dielectric and the channel interface.","abstract_has_math":false,"creators":["Opondo, Noah Felix Ochieng"],"institution":null,"degree_name":"Doctor of Philosophy (PhD)","degree_level":"Dissertation","degree_discipline":"Physics & Astronomy","degree_department":null,"school":null,"contributors":["SAEED MOHAMMADI","CHEN YANG","LUIS M KRUCZENSKI","GABOR A CSATHY"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2016,"date_issued":"2016-01-01T08:00:00Z","date_published":"2016-01-01T08:00:00Z","updated_at":"2026-07-24T03:54:38Z","subjects":["Field emitters","Germanium on Insulator","interface Trap density","Junctioless transistors","Low frequency noise","nanowire"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://docs.lib.purdue.edu/open_access_dissertations/1395","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["SAEED MOHAMMADI","CHEN YANG","LUIS M KRUCZENSKI","GABOR A CSATHY"]},{"key":"dc:creator","label":"Author","values":["Opondo, Noah Felix Ochieng"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"thesis:degree_discipline","label":"Discipline","values":["Physics & Astronomy"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Doctor of Philosophy (PhD)"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Field emitters","Germanium on Insulator","interface Trap density","Junctioless transistors","Low frequency noise","nanowire"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://docs.lib.purdue.edu/open_access_dissertations/1395"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Three different nanostructure active devices have been designed, fabricated and characterized. Junctionless transistors based on highly-doped silicon nanowires fabricated using a bottom-up fabrication approach are first discussed. The fabrication avoids the ion implantation step since silicon nanowires are doped in-situ during growth. Germanium junctionless transistors fabricated with a top down approach starting from a germanium on insulator substrate and using a gate stack of high-k dielectrics and GeO2 are also presented. The levels and origin of low-frequency noise in junctionless transistor devices fabricated from silicon nanowires and also from GeOI devices are reported. Low-frequency noise is an indicator of the quality of the material, hence its characterization can reveal the quality and perhaps reliability of fabricated transistors. A novel method based on low-frequency noise measurement to envisage trap density in the semiconductor bandgap near the semiconductor/oxide interface of nanoscale silicon junctionless transistors (JLTs) is presented. Low-frequency noise characterization of JLTs biased in saturation is conducted at different gate biases. The noise spectrum indicates either a Lorentzian or 1/f. A simple analysis of the low-frequency noise data leads to the density of traps and their energy within the semiconductor bandgap. The level of noise in silicon JLT devices is lower than reported values on transistors fabricated using a top-down approach. This noise level can be significantly improved by improving the quality of dielectric and the channel interface."]},{"key":"dc:title","label":"Title","values":["FABRICATION AND CHARACTERIZATION OF ACTIVE NANOSTRUCTURES"]}]}],"canonical_facts":{"dc:contributor":["SAEED MOHAMMADI","CHEN YANG","LUIS M KRUCZENSKI","GABOR A CSATHY"],"dc:creator":["Opondo, Noah Felix Ochieng"],"dc:description.abstract":["Three different nanostructure active devices have been designed, fabricated and characterized. Junctionless transistors based on highly-doped silicon nanowires fabricated using a bottom-up fabrication approach are first discussed. The fabrication avoids the ion implantation step since silicon nanowires are doped in-situ during growth. Germanium junctionless transistors fabricated with a top down approach starting from a germanium on insulator substrate and using a gate stack of high-k dielectrics and GeO2 are also presented. The levels and origin of low-frequency noise in junctionless transistor devices fabricated from silicon nanowires and also from GeOI devices are reported. Low-frequency noise is an indicator of the quality of the material, hence its characterization can reveal the quality and perhaps reliability of fabricated transistors. A novel method based on low-frequency noise measurement to envisage trap density in the semiconductor bandgap near the semiconductor/oxide interface of nanoscale silicon junctionless transistors (JLTs) is presented. Low-frequency noise characterization of JLTs biased in saturation is conducted at different gate biases. The noise spectrum indicates either a Lorentzian or 1/f. A simple analysis of the low-frequency noise data leads to the density of traps and their energy within the semiconductor bandgap. The level of noise in silicon JLT devices is lower than reported values on transistors fabricated using a top-down approach. This noise level can be significantly improved by improving the quality of dielectric and the channel interface."],"dc:identifier":["https://docs.lib.purdue.edu/open_access_dissertations/1395"],"dc:subject":["Field emitters","Germanium on Insulator","interface Trap density","Junctioless transistors","Low frequency noise","nanowire"],"dc:title":["FABRICATION AND CHARACTERIZATION OF ACTIVE NANOSTRUCTURES"],"thesis:degree_discipline":["Physics & Astronomy"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Doctor of Philosophy (PhD)"]},"updated_at":"2026-07-24T03:54:38Z"}