{"id":{"repo_id":"poli-torino","oai_identifier":"oai:iris.polito.it:11583/2983206"},"canonical_url":"https://search.dev.ndltd.org/etd/poli-torino/oai:iris.polito.it:11583/2983206","repository":{"repo_id":"poli-torino","name":"Politecnico di Torino","base_url":"https://iris.polito.it/oai/request"},"display":{"title":"VLSI ARCHITECTURES FOR VIDEO PROCESSING AND RISC-V","abstract":"L'abstract è presente nell'allegato / the abstract is in the attachment","abstract_html":"L'abstract è presente nell'allegato / the abstract is in the attachment","abstract_has_math":false,"creators":["WALID, WALID"],"institution":"Politecnico di Torino","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":["MARTINA, MAURIZIO","MASERA, Guido"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2023,"date_issued":"2023-10-09","date_published":"2023-10-09","updated_at":"2026-07-24T03:50:47Z","subjects":["Discriminative correlation filter · DSST · Real time · FPGA · QR · SVD · DFT · HOG · Video Encoding · AV1 · Wiener filter · VLSI · RISC-V · ISA · Super-scalar · CPU · Out-of-Order","Settore ING-INF/01 - Elettronica"],"languages":["eng"],"rights":["info:eu-repo/semantics/openAccess","license:Creative commons","license uri:http://creativecommons.org/licenses/by-nc-nd/4.0/"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/11583/2983206","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Walid, Walid","MARTINA, MAURIZIO","MASERA, Guido"]},{"key":"dc:creator","label":"Author","values":["WALID, WALID"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2023-10-09"]},{"key":"dc:publisher","label":"Institution","values":["Politecnico di Torino","country:Italy"]},{"key":"dc:relation","label":"Dc Relation","values":["firstpage:1","lastpage:128","numberofpages:128"]},{"key":"dc:type","label":"Dc Type","values":["info:eu-repo/semantics/doctoralThesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Discriminative correlation filter · DSST · Real time · FPGA · QR · SVD · DFT · HOG · Video Encoding · AV1 · Wiener filter · VLSI · RISC-V · ISA · Super-scalar · CPU · Out-of-Order","Settore ING-INF/01 - Elettronica"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["info:eu-repo/semantics/openAccess","license:Creative commons","license uri:http://creativecommons.org/licenses/by-nc-nd/4.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/11583/2983206"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["L'abstract è presente nell'allegato / the abstract is in the attachment"]},{"key":"dc:title","label":"Title","values":["VLSI ARCHITECTURES FOR VIDEO PROCESSING AND RISC-V"]}]}],"canonical_facts":{"dc:contributor":["Walid, Walid","MARTINA, MAURIZIO","MASERA, Guido"],"dc:creator":["WALID, WALID"],"dc:date":["2023-10-09"],"dc:description":["L'abstract è presente nell'allegato / the abstract is in the attachment"],"dc:identifier":["https://hdl.handle.net/11583/2983206"],"dc:language":["eng"],"dc:publisher":["Politecnico di Torino","country:Italy"],"dc:relation":["firstpage:1","lastpage:128","numberofpages:128"],"dc:rights":["info:eu-repo/semantics/openAccess","license:Creative commons","license uri:http://creativecommons.org/licenses/by-nc-nd/4.0/"],"dc:subject":["Discriminative correlation filter · DSST · Real time · FPGA · QR · SVD · DFT · HOG · Video Encoding · AV1 · Wiener filter · VLSI · RISC-V · ISA · Super-scalar · CPU · Out-of-Order","Settore ING-INF/01 - Elettronica"],"dc:title":["VLSI ARCHITECTURES FOR VIDEO PROCESSING AND RISC-V"],"dc:type":["info:eu-repo/semantics/doctoralThesis"]},"updated_at":"2026-07-24T03:50:47Z"}