{"id":{"repo_id":"poli-torino","oai_identifier":"oai:iris.polito.it:11583/2973429"},"canonical_url":"https://search.dev.ndltd.org/etd/poli-torino/oai:iris.polito.it:11583/2973429","repository":{"repo_id":"poli-torino","name":"Politecnico di Torino","base_url":"https://iris.polito.it/oai/request"},"display":{"title":"Modeling for the Computer-Aided Design of Long Interconnects","abstract":"L'abstract è presente nell'allegato / the abstract is in the attachment","abstract_html":"L'abstract è presente nell'allegato / the abstract is in the attachment","abstract_has_math":false,"creators":["TREVISO, FELIPE"],"institution":"Politecnico di Torino","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":["CANAVERO, Flavio","STIEVANO, IGOR SIMONE"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2022,"date_issued":"2022-11-14","date_published":"2022-11-14","updated_at":"2026-07-24T03:50:56Z","subjects":["kernel-based model","least-squares support vector machine","delay identification","delayed-rational model","machine learning","electrical interconnect modeling","Settore ING-IND/31 - Elettrotecnica"],"languages":["eng"],"rights":["info:eu-repo/semantics/openAccess","license:Creative commons","license uri:http://creativecommons.org/licenses/by-nc-nd/4.0/"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/11583/2973429","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Treviso, Felipe","CANAVERO, Flavio","STIEVANO, IGOR SIMONE"]},{"key":"dc:creator","label":"Author","values":["TREVISO, FELIPE"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2022-11-14"]},{"key":"dc:publisher","label":"Institution","values":["Politecnico di Torino","country:Italy"]},{"key":"dc:relation","label":"Dc Relation","values":["firstpage:1","lastpage:127","numberofpages:127"]},{"key":"dc:type","label":"Dc Type","values":["info:eu-repo/semantics/doctoralThesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["kernel-based model","least-squares support vector machine","delay identification","delayed-rational model","machine learning","electrical interconnect modeling","Settore ING-IND/31 - Elettrotecnica"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["info:eu-repo/semantics/openAccess","license:Creative commons","license uri:http://creativecommons.org/licenses/by-nc-nd/4.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/11583/2973429"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["L'abstract è presente nell'allegato / the abstract is in the attachment"]},{"key":"dc:title","label":"Title","values":["Modeling for the Computer-Aided Design of Long Interconnects"]}]}],"canonical_facts":{"dc:contributor":["Treviso, Felipe","CANAVERO, Flavio","STIEVANO, IGOR SIMONE"],"dc:creator":["TREVISO, FELIPE"],"dc:date":["2022-11-14"],"dc:description":["L'abstract è presente nell'allegato / the abstract is in the attachment"],"dc:identifier":["https://hdl.handle.net/11583/2973429"],"dc:language":["eng"],"dc:publisher":["Politecnico di Torino","country:Italy"],"dc:relation":["firstpage:1","lastpage:127","numberofpages:127"],"dc:rights":["info:eu-repo/semantics/openAccess","license:Creative commons","license uri:http://creativecommons.org/licenses/by-nc-nd/4.0/"],"dc:subject":["kernel-based model","least-squares support vector machine","delay identification","delayed-rational model","machine learning","electrical interconnect modeling","Settore ING-IND/31 - Elettrotecnica"],"dc:title":["Modeling for the Computer-Aided Design of Long Interconnects"],"dc:type":["info:eu-repo/semantics/doctoralThesis"]},"updated_at":"2026-07-24T03:50:56Z"}