Design, Analysis, and Testing of Memristive Logic and Authentication Architectures

The semiconductor industry is already undergoing drastic changes since the transistor-based devices scaling are approaching their physical limits. For example, current technology of the finFET is going towards 5nm. Hence, any variation of the channel size could produce undesirable effects, which brings challenges to addressing the problem. However, memristive devices as alternative emerging technologies have the capability to scale smaller geometrics and have found applications not only in high density memory design but also in neuromorphic systems, logic design, secure and crypto systems etc. Novel contribution of this thesis starts with a design of a low-complexity high-performance memristive multifunction logic architecture. This architecture is presented for low-power high-frequency operations in a single cycle, which does not require additional control input/logic and multucycle setup/operation. It can be seamlessly integrated with the existing CMOS technology with just one transistor and four memristors design and without additional overhead. This technique can realise both XOR/AND and XNOR/OR operations simultaneously. Experimental results prove that this technique significantly outperforms both CMOS and existing hybrid memristor-CMOS-based designs in terms of chip area, power consumption, and reliable performance especially at high frequencies. Then, we utilise our proposed logic architecture to design a delay-based arbiter physical unclonable function (PUF) by taking the memristive parasitic effects into consideration. The results prove that the proposed memristive arbiter PUF provides a good performance in terms of uniqueness, uniformity, bit-aliasing and reliability. However, most of the delay-based arbiter PUFs are suffering from the low resistance of the modelling attack because of their linearity. Hence, we leverage the non-linear behaviour of memristor to devise a low overhead architecture for replicating a source memristor to a destination memristor, which can also be used for non-linear encoding/decoding. Based on this architecture, we present a novel PUF framework. The PUF framework is tested by connecting the proposed architecture with two different digital-to-analogue conversion circuits respectively. We demonstrate the effectiveness of the architecture in Challenge-Response-Pair (CRP) based authentication, and for its physical uncloneability. This architecture is highly versatile and can be implemented with a single encoder or a number of encoders running in parallel for extending the sizes of CRPs. Finally, we subject our PUF architectures to machine learning based modelling attacks. We found out that the proposed PUF provides better resistance to such attacks, even for smaller bit sizes and at reduced overheads.

Grantor dc:publisher

Oxford Brookes University

Year dc:date

2021

Author dc:creator

• Yang, Xiaohan

Contributors dc:contributor

• Jabir, Abusaleh

Statement dc:rights

• All rights reserved

Language dc:language

en

DOI dc:identifier

https://doi.org/10.24384/qr7f-fr23

OAI identifier oai:identifier

tle:610fdaec-867e-4b7d-b93d-ec693dfc0aef:d6bd9758-527a-46cd-bfe2-c433766e8fca:1