Design, Analysis and Testing of Efficient Memristive Neural Networks

Neuromorphic systems are gaining signi cant importance in an era where CMOS digital techniques are reaching physical limits due to more power consumption, chip area and complex structures. Thus, memristors have appeared as promising devices not only in the area of neural systems but also in the elds of logic design, memory design, sensor and cryptography systems, etc. due to their non-volatility, nanoscale size and physical layout. We present memristor-based neural network designs and implementations in this work. This work rst simulates the di erent memristor modelling techniques in a high-level language (especially in C++). The multi-layer neural network is simulated based on this modelling. The results demonstrated that the linear and non-linear separable functions performed well with this modelling technique. This simulation modelling can be used to reduce the simulation time of very large memristor based neural networks. Then, an improved learning method for ex-situ training and a novel circuit design for activation function are also presented in this work. Based on these designs and learning methods, various single and multi-layer memristive crossbar neural architectures are implemented and tested in SPICE. Experimental results show that this learning method performed e ciently while implementing memristor-based neural networks in ex-situ. The results also demonstrated that the memristive crossbar-based multilayer neural networks with the proposed circuit occupy less chip area as compared to existing circuit designs used for activation functions. Lastly,this work analyses the fault tolerance behaviours of memristor-based neural networks and evaluates the yield of memristor crossbar array-based neural networks using the Markov chains. The repairability process is also considered while evaluating the yield. Our analysis also shows that a well-designed network can function e ectively with up to 50% faulty memristors with negligible impact on the learning capabilities of the network. The analysis is useful when designing a network with redundancy. The results also show that the yield can be improved with redundancies and a higher ratio of SA0 faults.

Grantor dc:publisher

Oxford Brookes University

Year dc:date

2022

Author dc:creator

• Bala, Anu

Contributors dc:contributor

• Jabir, Abusaleh

Statement dc:rights

• All rights reserved

Language dc:language

en

DOI dc:identifier

https://doi.org/10.24384/4x1d-3j19

OAI identifier oai:identifier

tle:18df6bd5-9ec1-484f-9a7d-2af2c71914b7:d6bd9758-527a-46cd-bfe2-c433766e8fca:1