Scaling technology has resulted in increased leakage power consumption in VLSI circuits. Even though there are several power consumption reduction techniques in the industry today, the increasing leakage power consumption in the deep submicron CMOS technologies has manifested the need for more aggressive control mechanisms. Runtime Active Leakage Control (RALC) techniques like Power Gating (PG) and Reverse Body Biasing (RBB) being the primary candidates for RALC, PG is found to give better leakage savings than RBB and hence is a popular technique in the industry.
Comparing PG and RBB techniques, RBB has less overhead and average leakage savings. Though PG achieves high leakage savings, the overhead is high. This research starts from the basic question of how the leakage savings with RBB can be improved and extensively applied on present day circuits. One such proposal is a novel RBB technique of Light Vth hopping (LITHE) which varies in the voltage used for body biasing which is done with the intention of reducing the Energy Breakeven Time (EBT) of the circuit, leading to frequent application of RBB. With LITHE as a starting point, the key objective of this work is to address several problems that might arise during integration of LITHE in an industrial design flow.
The thesis proposes a generic flow from RTL to SPICE that incorporates LITHE technique at near optimum granularity. This concept has been expanded to sequential circuits and the problems of control transistor sizing and control signal generation have also been addressed. Also proposed is a clustering algorithm to integrate LITHE with clock gating in sequential circuits. The entire flow has been tested on a 90nm library which can support a dierent body bias. The flow has been veried on RTLs of logic designs with varying complexities and the applicability of temporal and spatial idleness exploration principles have also been analyzed.
","abstract_html":"<p>Scaling technology has resulted in increased leakage power consumption in VLSI circuits. Even though there are several power consumption reduction techniques in the industry today, the increasing leakage power consumption in the deep submicron CMOS technologies has manifested the need for more aggressive control mechanisms. Runtime Active Leakage Control (RALC) techniques like Power Gating (PG) and Reverse Body Biasing (RBB) being the primary candidates for RALC, PG is found to give better leakage savings than RBB and hence is a popular technique in the industry.</p><p> Comparing PG and RBB techniques, RBB has less overhead and average leakage savings. Though PG achieves high leakage savings, the overhead is high. This research starts from the basic question of how the leakage savings with RBB can be improved and extensively applied on present day circuits. One such proposal is a novel RBB technique of Light Vth hopping (LITHE) which varies in the voltage used for body biasing which is done with the intention of reducing the Energy Breakeven Time (EBT) of the circuit, leading to frequent application of RBB. With LITHE as a starting point, the key objective of this work is to address several problems that might arise during integration of LITHE in an industrial design flow.</p><p>The thesis proposes a generic flow from RTL to SPICE that incorporates LITHE technique at near optimum granularity. This concept has been expanded to sequential circuits and the problems of control transistor sizing and control signal generation have also been addressed. Also proposed is a clustering algorithm to integrate LITHE with clock gating in sequential circuits. The entire flow has been tested on a 90nm library which can support a dierent body bias. The flow has been veried on RTLs of logic designs with varying complexities and the applicability of temporal and spatial idleness exploration principles have also been analyzed.</p>","abstract_has_math":false,"creators":["Balasubramanian, Venkat Krishnan"],"institution":"University of Cincinnati","degree_name":"MS","degree_level":"masters","degree_discipline":"Engineering and Applied Science: Computer Engineering","degree_department":null,"school":null,"contributors":["Vemuri, Ranganadha"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2012,"date_issued":"2012","date_published":"2012","updated_at":"2026-07-24T03:36:23Z","subjects":["Computer Engineering","Leakage Reduction","Low Power","Light Vth Hopping"],"languages":["English"],"rights":["unrestricted","This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws."],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://rave.ohiolink.edu/etdc/view?acc_num=ucin1352490620","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Vemuri, Ranganadha"]},{"key":"dc:creator","label":"Author","values":["Balasubramanian, Venkat Krishnan"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2012"]},{"key":"dc:publisher","label":"Institution","values":["University of Cincinnati / OhioLINK"]},{"key":"dc:type","label":"Dc Type","values":["Electronic Thesis or Dissertation"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Engineering and Applied Science: Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["MS"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Cincinnati"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Engineering","Leakage Reduction","Low Power","Light Vth Hopping"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["English"]},{"key":"dc:rights","label":"Dc Rights","values":["unrestricted","This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws."]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://rave.ohiolink.edu/etdc/view?acc_num=ucin1352490620"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Scaling technology has resulted in increased leakage power consumption in VLSI circuits. Even though there are several power consumption reduction techniques in the industry today, the increasing leakage power consumption in the deep submicron CMOS technologies has manifested the need for more aggressive control mechanisms. Runtime Active Leakage Control (RALC) techniques like Power Gating (PG) and Reverse Body Biasing (RBB) being the primary candidates for RALC, PG is found to give better leakage savings than RBB and hence is a popular technique in the industry.
Comparing PG and RBB techniques, RBB has less overhead and average leakage savings. Though PG achieves high leakage savings, the overhead is high. This research starts from the basic question of how the leakage savings with RBB can be improved and extensively applied on present day circuits. One such proposal is a novel RBB technique of Light Vth hopping (LITHE) which varies in the voltage used for body biasing which is done with the intention of reducing the Energy Breakeven Time (EBT) of the circuit, leading to frequent application of RBB. With LITHE as a starting point, the key objective of this work is to address several problems that might arise during integration of LITHE in an industrial design flow.
The thesis proposes a generic flow from RTL to SPICE that incorporates LITHE technique at near optimum granularity. This concept has been expanded to sequential circuits and the problems of control transistor sizing and control signal generation have also been addressed. Also proposed is a clustering algorithm to integrate LITHE with clock gating in sequential circuits. The entire flow has been tested on a 90nm library which can support a dierent body bias. The flow has been veried on RTLs of logic designs with varying complexities and the applicability of temporal and spatial idleness exploration principles have also been analyzed.
"]},{"key":"dc:format","label":"Dc Format","values":["application/pdf","p.95","2.48 MB"]},{"key":"dc:title","label":"Title","values":["Design Automation Flow for Voltage Adaptive Light Vth Hopping for Leakage Minimization in Sequential Circuits"]}]}],"canonical_facts":{"dc:contributor":["Vemuri, Ranganadha"],"dc:creator":["Balasubramanian, Venkat Krishnan"],"dc:date":["2012"],"dc:description":["Scaling technology has resulted in increased leakage power consumption in VLSI circuits. Even though there are several power consumption reduction techniques in the industry today, the increasing leakage power consumption in the deep submicron CMOS technologies has manifested the need for more aggressive control mechanisms. Runtime Active Leakage Control (RALC) techniques like Power Gating (PG) and Reverse Body Biasing (RBB) being the primary candidates for RALC, PG is found to give better leakage savings than RBB and hence is a popular technique in the industry.
Comparing PG and RBB techniques, RBB has less overhead and average leakage savings. Though PG achieves high leakage savings, the overhead is high. This research starts from the basic question of how the leakage savings with RBB can be improved and extensively applied on present day circuits. One such proposal is a novel RBB technique of Light Vth hopping (LITHE) which varies in the voltage used for body biasing which is done with the intention of reducing the Energy Breakeven Time (EBT) of the circuit, leading to frequent application of RBB. With LITHE as a starting point, the key objective of this work is to address several problems that might arise during integration of LITHE in an industrial design flow.
The thesis proposes a generic flow from RTL to SPICE that incorporates LITHE technique at near optimum granularity. This concept has been expanded to sequential circuits and the problems of control transistor sizing and control signal generation have also been addressed. Also proposed is a clustering algorithm to integrate LITHE with clock gating in sequential circuits. The entire flow has been tested on a 90nm library which can support a dierent body bias. The flow has been veried on RTLs of logic designs with varying complexities and the applicability of temporal and spatial idleness exploration principles have also been analyzed.
"],"dc:format":["application/pdf","p.95","2.48 MB"],"dc:identifier":["http://rave.ohiolink.edu/etdc/view?acc_num=ucin1352490620"],"dc:language":["English"],"dc:publisher":["University of Cincinnati / OhioLINK"],"dc:rights":["unrestricted","This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws."],"dc:subject":["Computer Engineering","Leakage Reduction","Low Power","Light Vth Hopping"],"dc:title":["Design Automation Flow for Voltage Adaptive Light Vth Hopping for Leakage Minimization in Sequential Circuits"],"dc:type":["Electronic Thesis or Dissertation"],"thesis:degree_discipline":["Engineering and Applied Science: Computer Engineering"],"thesis:degree_level":["masters"],"thesis:degree_name":["MS"],"thesis:institution_name":["University of Cincinnati"]},"updated_at":"2026-07-24T03:36:23Z"}