{"id":{"repo_id":"ohiolink","oai_identifier":"oai:etd.ohiolink.edu:osu1366206443"},"canonical_url":"https://search.dev.ndltd.org/etd/ohiolink/oai:etd.ohiolink.edu:osu1366206443","repository":{"repo_id":"ohiolink","name":"OhioLINK","base_url":"https://etd.ohiolink.edu/acprod/odb_etd/ws/oai/oai"},"display":{"title":"Characterization and Modeling of Low Frequency Noise and Dielectric Traps in Scaled MOSFET Devices","abstract":"CMOS scaling has pushed the industry toward circuits and systems of better performance, higher density, and lower cost for electronic products through the past several decades. The high-K materials are introduced into the MOSFET structure to reduce the gate leakage current, increase the gate capacitance for current drive and reduce short channel effects. However, the oxide trap density in these materials is intrinsically higher and that leads to stronger trapping effects. This dissertation describes the modeling and electrical characterization of nanoscaled high-K and SiON MOSFET devices, focusing on their trap-related device performances. Research work on performance characterization of carbon ion implantation in advanced CMOS replacement technology is also included pursuing a cost-effective approach for precise control of vertical dopant profile.We develop a quantum mechanical treatment of low-frequency noise to extend the ``unified'' noise model and includes remote Coulomb scattering and surface roughness - the latter is a new consideration in the theory. Our experimental work focuses on scaled NMOS devices with a composite dielectric consisting of a 0.5 nm SiO2 covered with a high-K, 1.6 nm HfO2 with a metal gate. In the past, Coulomb scattering was assumed to arise from trapping centers located at the Si-SiO2 interface; however, this cannot give rise to a 1/f noise spectrum. We model remote Coulomb scattering into the dielectric film as traps in these films easily lie within a tunneling distance from the interface. This approach explains the decrease in the remote Coulomb scattering parameter ('alpha') as a function of gate voltage. In addition, we introduce surface roughness scattering through fluctuations in the normal electric field due to fluctuations in the free carrier density with a surface scattering parameter ('beta') proportional to the SPICE surface roughness parameter 'thetaS'. Good agreement is obtained between our model and experimental results for both IDS - VGS and the power spectral density, SId, characteristics in very strong inversion region where the surface quantization of the 2D subbands is strong.Characterization on SiON MOSFET devices are performed including I-V (Current-Voltage), C-V (Capacitance-Voltage), charge pumping etc. NMOS transistors exhibit a higher interface trap density (9.7E10 cm-2eV-1) than PMOS (5.8E10 cm-2eV-1). The mean capture cross sections are comparable in these devcies: 3.3E-17 cm2 and 9.1E-17 cm2, receptively, for CMOS devices. Different mobility extraction methods are presented and the results indicate strong surface roughness scattering in these devices.The effects of channel carbon ion implantation (Cii) on advanced high-K metal gate low-power CMOS devices have been studies. Cii improves the device performance, especially for NMOS. The improvement comes mainly from an improvement in electron mobility, where Coulomb scattering is reduced due to retarded boron diffusion with carbon.","abstract_html":"CMOS scaling has pushed the industry toward circuits and systems of better performance, higher density, and lower cost for electronic products through the past several decades. The high-K materials are introduced into the MOSFET structure to reduce the gate leakage current, increase the gate capacitance for current drive and reduce short channel effects. However, the oxide trap density in these materials is intrinsically higher and that leads to stronger trapping effects. This dissertation describes the modeling and electrical characterization of nanoscaled high-K and SiON MOSFET devices, focusing on their trap-related device performances. Research work on performance characterization of carbon ion implantation in advanced CMOS replacement technology is also included pursuing a cost-effective approach for precise control of vertical dopant profile.We develop a quantum mechanical treatment of low-frequency noise to extend the ``unified'' noise model and includes remote Coulomb scattering and surface roughness - the latter is a new consideration in the theory. Our experimental work focuses on scaled NMOS devices with a composite dielectric consisting of a 0.5 nm SiO<sub>2</sub> covered with a high-K, 1.6 nm HfO<sub>2</sub> with a metal gate. In the past, Coulomb scattering was assumed to arise from trapping centers located at the Si-SiO<sub>2</sub> interface; however, this cannot give rise to a 1/f noise spectrum. We model remote Coulomb scattering into the dielectric film as traps in these films easily lie within a tunneling distance from the interface. This approach explains the decrease in the remote Coulomb scattering parameter ('alpha') as a function of gate voltage. In addition, we introduce surface roughness scattering through fluctuations in the normal electric field due to fluctuations in the free carrier density with a surface scattering parameter ('beta') proportional to the SPICE surface roughness parameter 'theta<sub>S</sub>'. Good agreement is obtained between our model and experimental results for both I<sub>DS</sub> - V<sub>GS</sub> and the power spectral density, S<sub>Id</sub>, characteristics in very strong inversion region where the surface quantization of the 2D subbands is strong.Characterization on SiON MOSFET devices are performed including I-V (Current-Voltage), C-V (Capacitance-Voltage), charge pumping etc. NMOS transistors exhibit a higher interface trap density (9.7E10 cm<sup>-2</sup>eV<sup>-1</sup>) than PMOS (5.8E10 cm<sup>-2</sup>eV<sup>-1</sup>). The mean capture cross sections are comparable in these devcies: 3.3E-17 cm<sup>2</sup> and 9.1E-17 cm<sup>2</sup>, receptively, for CMOS devices. Different mobility extraction methods are presented and the results indicate strong surface roughness scattering in these devices.The effects of channel carbon ion implantation (Cii) on advanced high-K metal gate low-power CMOS devices have been studies. Cii improves the device performance, especially for NMOS. The improvement comes mainly from an improvement in electron mobility, where Coulomb scattering is reduced due to retarded boron diffusion with carbon.","abstract_has_math":false,"creators":["Zhang, Xiaochen"],"institution":"The Ohio State University","degree_name":"Doctor of Philosophy","degree_level":"doctoral","degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":["White, Marvin"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013-07-24","date_published":"2013-07-24","updated_at":"2026-07-24T03:37:46Z","subjects":["Electrical Engineering"],"languages":["English"],"rights":["unrestricted","This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws."],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://rave.ohiolink.edu/etdc/view?acc_num=osu1366206443","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["White, Marvin"]},{"key":"dc:creator","label":"Author","values":["Zhang, Xiaochen"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2013-07-24"]},{"key":"dc:publisher","label":"Institution","values":["The Ohio State University / OhioLINK"]},{"key":"dc:type","label":"Dc Type","values":["Electronic Thesis or Dissertation"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["doctoral"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Doctor of Philosophy"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["The Ohio State University"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrical Engineering"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["English"]},{"key":"dc:rights","label":"Dc Rights","values":["unrestricted","This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws."]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://rave.ohiolink.edu/etdc/view?acc_num=osu1366206443"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["CMOS scaling has pushed the industry toward circuits and systems of better performance, higher density, and lower cost for electronic products through the past several decades. The high-K materials are introduced into the MOSFET structure to reduce the gate leakage current, increase the gate capacitance for current drive and reduce short channel effects. However, the oxide trap density in these materials is intrinsically higher and that leads to stronger trapping effects. This dissertation describes the modeling and electrical characterization of nanoscaled high-K and SiON MOSFET devices, focusing on their trap-related device performances. Research work on performance characterization of carbon ion implantation in advanced CMOS replacement technology is also included pursuing a cost-effective approach for precise control of vertical dopant profile.We develop a quantum mechanical treatment of low-frequency noise to extend the ``unified'' noise model and includes remote Coulomb scattering and surface roughness - the latter is a new consideration in the theory. Our experimental work focuses on scaled NMOS devices with a composite dielectric consisting of a 0.5 nm SiO2 covered with a high-K, 1.6 nm HfO2 with a metal gate. In the past, Coulomb scattering was assumed to arise from trapping centers located at the Si-SiO2 interface; however, this cannot give rise to a 1/f noise spectrum. We model remote Coulomb scattering into the dielectric film as traps in these films easily lie within a tunneling distance from the interface. This approach explains the decrease in the remote Coulomb scattering parameter ('alpha') as a function of gate voltage. In addition, we introduce surface roughness scattering through fluctuations in the normal electric field due to fluctuations in the free carrier density with a surface scattering parameter ('beta') proportional to the SPICE surface roughness parameter 'thetaS'. Good agreement is obtained between our model and experimental results for both IDS - VGS and the power spectral density, SId, characteristics in very strong inversion region where the surface quantization of the 2D subbands is strong.Characterization on SiON MOSFET devices are performed including I-V (Current-Voltage), C-V (Capacitance-Voltage), charge pumping etc. NMOS transistors exhibit a higher interface trap density (9.7E10 cm-2eV-1) than PMOS (5.8E10 cm-2eV-1). The mean capture cross sections are comparable in these devcies: 3.3E-17 cm2 and 9.1E-17 cm2, receptively, for CMOS devices. Different mobility extraction methods are presented and the results indicate strong surface roughness scattering in these devices.The effects of channel carbon ion implantation (Cii) on advanced high-K metal gate low-power CMOS devices have been studies. Cii improves the device performance, especially for NMOS. The improvement comes mainly from an improvement in electron mobility, where Coulomb scattering is reduced due to retarded boron diffusion with carbon."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf","3.84 MB"]},{"key":"dc:title","label":"Title","values":["Characterization and Modeling of Low Frequency Noise and Dielectric Traps in Scaled MOSFET Devices"]}]}],"canonical_facts":{"dc:contributor":["White, Marvin"],"dc:creator":["Zhang, Xiaochen"],"dc:date":["2013-07-24"],"dc:description":["CMOS scaling has pushed the industry toward circuits and systems of better performance, higher density, and lower cost for electronic products through the past several decades. The high-K materials are introduced into the MOSFET structure to reduce the gate leakage current, increase the gate capacitance for current drive and reduce short channel effects. However, the oxide trap density in these materials is intrinsically higher and that leads to stronger trapping effects. This dissertation describes the modeling and electrical characterization of nanoscaled high-K and SiON MOSFET devices, focusing on their trap-related device performances. Research work on performance characterization of carbon ion implantation in advanced CMOS replacement technology is also included pursuing a cost-effective approach for precise control of vertical dopant profile.We develop a quantum mechanical treatment of low-frequency noise to extend the ``unified'' noise model and includes remote Coulomb scattering and surface roughness - the latter is a new consideration in the theory. Our experimental work focuses on scaled NMOS devices with a composite dielectric consisting of a 0.5 nm SiO2 covered with a high-K, 1.6 nm HfO2 with a metal gate. In the past, Coulomb scattering was assumed to arise from trapping centers located at the Si-SiO2 interface; however, this cannot give rise to a 1/f noise spectrum. We model remote Coulomb scattering into the dielectric film as traps in these films easily lie within a tunneling distance from the interface. This approach explains the decrease in the remote Coulomb scattering parameter ('alpha') as a function of gate voltage. In addition, we introduce surface roughness scattering through fluctuations in the normal electric field due to fluctuations in the free carrier density with a surface scattering parameter ('beta') proportional to the SPICE surface roughness parameter 'thetaS'. Good agreement is obtained between our model and experimental results for both IDS - VGS and the power spectral density, SId, characteristics in very strong inversion region where the surface quantization of the 2D subbands is strong.Characterization on SiON MOSFET devices are performed including I-V (Current-Voltage), C-V (Capacitance-Voltage), charge pumping etc. NMOS transistors exhibit a higher interface trap density (9.7E10 cm-2eV-1) than PMOS (5.8E10 cm-2eV-1). The mean capture cross sections are comparable in these devcies: 3.3E-17 cm2 and 9.1E-17 cm2, receptively, for CMOS devices. Different mobility extraction methods are presented and the results indicate strong surface roughness scattering in these devices.The effects of channel carbon ion implantation (Cii) on advanced high-K metal gate low-power CMOS devices have been studies. Cii improves the device performance, especially for NMOS. The improvement comes mainly from an improvement in electron mobility, where Coulomb scattering is reduced due to retarded boron diffusion with carbon."],"dc:format":["application/pdf","3.84 MB"],"dc:identifier":["http://rave.ohiolink.edu/etdc/view?acc_num=osu1366206443"],"dc:language":["English"],"dc:publisher":["The Ohio State University / OhioLINK"],"dc:rights":["unrestricted","This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws."],"dc:subject":["Electrical Engineering"],"dc:title":["Characterization and Modeling of Low Frequency Noise and Dielectric Traps in Scaled MOSFET Devices"],"dc:type":["Electronic Thesis or Dissertation"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_level":["doctoral"],"thesis:degree_name":["Doctor of Philosophy"],"thesis:institution_name":["The Ohio State University"]},"updated_at":"2026-07-24T03:37:46Z"}