Correlator for a Basis-Space Architecture Ultra-Wideband Receiver

Ultra Wideband (UWB) signals have great potential for high data transmission and precise location. However, their wide bandwidth and low signal to noise levels make UWB receiver design via traditional methods difficult. New receiver architectures have been proposed that rely on the correlation of the received signal and a set of basis functions to reduce the sampling requirement below Nyquist. Correlation is accomplished as the wide bandwidth received signal is projected over bases via a multiply-integrate function. Critical to this correlation operation in the new receivers is a resettable integrator function used to generate an inner product of the sampling basis and the received signal. This thesis develops a circuit architecture to accomplish the projection via a wideband integrator. The type of UWB signal for evaluation of the integrator is multi-band orthogonal frequency division multiplexing (MB-OFDM).Architecture development for the integrator begins with a comparison of ideal integration versus circuit limited real integration. Ideal integration relies on infinite DC gain and constant phase shift to operate. Real integration is constrained by the limited DC gain and parasitic poles inherent in circuit implementation. Optimum real integration requires high gain and wide bandwidth circuits which are competing goals in a deep submicron technology. To relax the requirements of gain and bandwidth while still producing wideband integration, the proposed integrator architecture spreads integration of the received signal in both frequency and time. Frequency spread is accomplished via channelization and time spread is accomplished by a sequence of resettable gm-C integration blocks. The architecture is analyzed for both its ability to handle high peak to average power and low signal to noise ratio signals.An initial implementation of the architecture was constructed in an RF compatible process to identify circuit and process limitations and create a proof of concept for the architecture. Process characterization for the 0.13$um RF process showed that square-law assumptions were not valid for constructing circuits. Instead, a design point approach was used. Individual circuits in the initial implementation are detailed in the thesis and include a wide bandwidth two stage op-amp and a current-mirror transconductor. These circuits create a time-spreading integrator circuit capable of integrating 6-100Mhz of bandwidth with up to a 5ns integration timeperiod. The implementation highlighted the 36dB gain of the transconductor and th 590MHz unity gain of the amplifier as critical limiting factors in the implementation. Post fabrication, a test environment was constructed using an FPGA to examine a single integrator's performance for a single frequency tone and uncover problems in the implementation. The test platform showed a 250mV peak-to-peak stepwise integrated output for a 40mV peak-to-peak 20MHz input sine wave. Based on the results of the initial circuit design effort and the test environment evaluation, recommendations for circuit and test environment modifications are proposed. Proposed circuit modifications address transconductor bandwidth support and linearity as well as reference voltage susceptibility. Additional amplify-hold blocks are also added to the implementation to relax settling time and ease integration capacitor reset. Finally, a basis-receiver experimental apparatus is introduced to further characterize the architecture's ability to handle wide-bandwidth projection over arbitrary bases and to explore the capacity of the channelized integrator to utilize low power non-RF mixing.

Name thesis:degree_name

Doctor of Philosophy

Level thesis:degree_level

doctoral

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor dc:publisher

The Ohio State University

Year dc:date

2013

Author dc:creator

• Dupaix, Brian P.

Contributors dc:contributor

• Bibyk, Steven

• Electrical Engineering
• Ultrawideband
• CMOS circuit design
• Integration

Statement dc:rights

• unrestricted
• This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.

Language dc:language

English

Repository record dc:identifier

http://rave.ohiolink.edu/etdc/view?acc_num=osu1366199620

OAI identifier oai:identifier

oai:etd.ohiolink.edu:osu1366199620