{"id":{"repo_id":"ohiolink","oai_identifier":"oai:etd.ohiolink.edu:case1365198486"},"canonical_url":"https://search.dev.ndltd.org/etd/ohiolink/oai:etd.ohiolink.edu:case1365198486","repository":{"repo_id":"ohiolink","name":"OhioLINK","base_url":"https://etd.ohiolink.edu/acprod/odb_etd/ws/oai/oai"},"display":{"title":"Energy Efficient Computing in FPGA Through Embedded RAM Blocks","abstract":"FPGAs have emerged as the preferred prototyping and accelerator platform for diverseapplication domains like digital signal processing (DSP), security, and multimedia having real time performance requirements. Applications in these domains are often dominated by complex compute-intensive operations requiring implementation of complex datapaths or functions e.g. transcendental functions. Conventional spatial mapping of theseoperations to the configurable logic blocks (CLBs) or embedded DSP blocks of a FPGA device imposes a major bottleneck in energy efficiency. In this thesis, we propose to use embedded memory blocks (EMBs) in FPGA for energy-efficient mapping of these operations. We select appropriate parts of an application for mapping into embedded memory blocks in a heterogeneous mapping framework that aims at maximizing energy efficiency. Complex operations are decomposed / fused into large multi-input multi-output look-up tables, mapped into EMBs and evaluated through sequential access of them. Optimal energy configuration of the embedded memory blocks are determined and effectiveness of the proposed methodology is evaluated for a set of common applications using a commercial state-of-the-art FPGA system (Altera Stratix IV). The proposed work also builds a strategy for energy-accuracy trade-off for multimedia applications and leverages the effectiveness of memory based computing in FPGA for such approximate computations.","abstract_html":"FPGAs have emerged as the preferred prototyping and accelerator platform for diverseapplication domains like digital signal processing (DSP), security, and multimedia having real time performance requirements. Applications in these domains are often dominated by complex compute-intensive operations requiring implementation of complex datapaths or functions e.g. transcendental functions. Conventional spatial mapping of theseoperations to the configurable logic blocks (CLBs) or embedded DSP blocks of a FPGA device imposes a major bottleneck in energy efficiency. In this thesis, we propose to use embedded memory blocks (EMBs) in FPGA for energy-efficient mapping of these operations. We select appropriate parts of an application for mapping into embedded memory blocks in a heterogeneous mapping framework that aims at maximizing energy efficiency. Complex operations are decomposed / fused into large multi-input multi-output look-up tables, mapped into EMBs and evaluated through sequential access of them. Optimal energy configuration of the embedded memory blocks are determined and effectiveness of the proposed methodology is evaluated for a set of common applications using a commercial state-of-the-art FPGA system (Altera Stratix IV). The proposed work also builds a strategy for energy-accuracy trade-off for multimedia applications and leverages the effectiveness of memory based computing in FPGA for such approximate computations.","abstract_has_math":false,"creators":["Ghosh, Anandaroop"],"institution":"Case Western Reserve University School of Graduate Studies","degree_name":"Master of Sciences","degree_level":"masters","degree_discipline":"EECS - Computer Engineering","degree_department":null,"school":null,"contributors":["Bhunia, Swarup"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013-08-16","date_published":"2013-08-16","updated_at":"2026-07-24T03:37:31Z","subjects":["Computer Engineering","FPGA","Memory Based Computing","Energy Efficient Computing"],"languages":["English"],"rights":["unrestricted","This thesis or dissertation is protected by copyright: all rights reserved. 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In this thesis, we propose to use embedded memory blocks (EMBs) in FPGA for energy-efficient mapping of these operations. We select appropriate parts of an application for mapping into embedded memory blocks in a heterogeneous mapping framework that aims at maximizing energy efficiency. Complex operations are decomposed / fused into large multi-input multi-output look-up tables, mapped into EMBs and evaluated through sequential access of them. Optimal energy configuration of the embedded memory blocks are determined and effectiveness of the proposed methodology is evaluated for a set of common applications using a commercial state-of-the-art FPGA system (Altera Stratix IV). The proposed work also builds a strategy for energy-accuracy trade-off for multimedia applications and leverages the effectiveness of memory based computing in FPGA for such approximate computations."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf","p.64","1.38 MB"]},{"key":"dc:title","label":"Title","values":["Energy Efficient Computing in FPGA Through Embedded RAM Blocks"]}]}],"canonical_facts":{"dc:contributor":["Bhunia, Swarup"],"dc:creator":["Ghosh, Anandaroop"],"dc:date":["2013-08-16"],"dc:description":["FPGAs have emerged as the preferred prototyping and accelerator platform for diverseapplication domains like digital signal processing (DSP), security, and multimedia having real time performance requirements. Applications in these domains are often dominated by complex compute-intensive operations requiring implementation of complex datapaths or functions e.g. transcendental functions. Conventional spatial mapping of theseoperations to the configurable logic blocks (CLBs) or embedded DSP blocks of a FPGA device imposes a major bottleneck in energy efficiency. In this thesis, we propose to use embedded memory blocks (EMBs) in FPGA for energy-efficient mapping of these operations. We select appropriate parts of an application for mapping into embedded memory blocks in a heterogeneous mapping framework that aims at maximizing energy efficiency. Complex operations are decomposed / fused into large multi-input multi-output look-up tables, mapped into EMBs and evaluated through sequential access of them. Optimal energy configuration of the embedded memory blocks are determined and effectiveness of the proposed methodology is evaluated for a set of common applications using a commercial state-of-the-art FPGA system (Altera Stratix IV). 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