Design and Modeling Environment for Nano-Electro-Mechanical Switch (NEMS) Digital Systems

In this thesis, we study models for an innovative type of Nano-Electro-Mechanical Switch (NEMS) at the physical, logical and circuit level. NEMS are switching devices, which have virtually zero leakage current, 1-3 V operation voltage, 1-10 ns switching time, and small footprint. NEMS switches can be easily hybridized with CMOS at the metallization or device levels to manage leakage current and power. Our fabricated NEMS switches enable the implementation of a digital switching function using four times fewer switches than traditional approaches. In particular, the design of basic two-input logic gates (AND, OR, NAND, NOR, XOR, XNOR, NOT and BUF) can be implemented on a single NEMS switch. We design a compact and ultra-low power NEMS FPGA using these devices. The FPGA implementation uses a four-input CLB, which requires only eight NEMS switches and at most two mechanical delays per computation. In contrast, CMOS CLBs require over 150 traditional switches. By reducing the number of devices, our approach improves yield, reproducibility, speed, and power and simplifies the implementation. To accurately evaluate the performance of NEMS digital systems, we derive a SPICE circuit simulation model (Macromodel) that allows the evaluation of the NEMS based systems using fast circuit simulation techniques with the same accuracy of a slow multi-physics 3D Finite Element Analysis (FEA) model. The 3D FEA model is constructed to capture the multi-physics phenomena of the switches using the FEA simulation tool (COMSOL Multi-physics). The 3D FEA model is calibrated using the fabricated device measurements. This ensures that the 3D FEA physical device model produces the results that are similar to the results obtained from the fabricated device measurements. Using the 3D FEA physical model, we present a procedure to extract mechanical parameters which are used in developing the mechanical lumped model. The NEMS Macromodel is integrated into a circuit simulator enabling the evaluation of NEMS devices in an electrical design environment. The accuracy of the NEMS Macromodel is verified using the device properties derived from the 3D FEA models and measured from the fabricated devices. Using the circuit simulator, we measure the power dissipation of NEMS designs and compare them to the CMOS digital designs. Our experiment shows three to four times of magnitude improvement in power reduction for the NEMS technology over CMOS. This technology could be an alternative technology in implementing portable battery-power systems that are limited by the battery life and the ambient environments.

Name thesis:degree_name

Doctor of Philosophy

Level thesis:degree_level

doctoral

Discipline thesis:degree_discipline

EECS - Computer Engineering

Grantor dc:publisher

Case Western Reserve University School of Graduate Studies

Year dc:date

2013

Author dc:creator

• Han, Sijing

Contributors dc:contributor

• Saab, Daniel

• Computer Engineering
• NEMS
• low power
• digital circuit design
• FPGA design
• 3D FEA model
• circuit simulation model

Statement dc:rights

• unrestricted
• This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.

Language dc:language

English

Repository record dc:identifier

http://rave.ohiolink.edu/etdc/view?acc_num=case1354568246

OAI identifier oai:identifier

oai:etd.ohiolink.edu:case1354568246