{"id":{"repo_id":"ohiolink","oai_identifier":"oai:etd.ohiolink.edu:akron1363233037"},"canonical_url":"https://search.dev.ndltd.org/etd/ohiolink/oai:etd.ohiolink.edu:akron1363233037","repository":{"repo_id":"ohiolink","name":"OhioLINK","base_url":"https://etd.ohiolink.edu/acprod/odb_etd/ws/oai/oai"},"display":{"title":"Digital Hardware Architectures for Exact and Approximate DCT Computation Using Number Theoretic Techniques","abstract":"The discrete cosine transform (DCT) is a key tool in many image and video coding applications. Therefore significant effort is been made to realize DCT computation utilizing minimum resources in terms of hardware, at acceptable accuracy. This thesis explores the use of number theoretic techniques such as algebraic integer (AI) encoding and expansion factor methods for exact and approximate DCT computation. Novel digital hardware architectures that utilize these techniques to obtain, a) improvements in accuracy b) reductions in area and power consumption, are proposed. Review of the utilized number theoretic techniques, mathematical derivations of the proposed architectures and digital hardware implementations are provided. All designs are implemented and tested on-chip using field programmable gate array (FPGA) technology and also simulated up to synthesis level for application specific integrated circuits (ASICs). Obtained accuracy and hardware metrics are presented and compared with the current state-of-the-art. Performance of AI based DCT computation algorithms in next generation video codecs are also analysed by integrating the proposed algorithms into high efficiency video coding standard (HEVC). The proposed digital architectures have potential applications in multimedia, automaticsurveillance, geospatial remote sensing, and automotive industry.","abstract_html":"The discrete cosine transform (DCT) is a key tool in many image and video coding applications. Therefore significant effort is been made to realize DCT computation utilizing minimum resources in terms of hardware, at acceptable accuracy. This thesis explores the use of number theoretic techniques such as algebraic integer (AI) encoding and expansion factor methods for exact and approximate DCT computation. Novel digital hardware architectures that utilize these techniques to obtain, a) improvements in accuracy b) reductions in area and power consumption, are proposed. Review of the utilized number theoretic techniques, mathematical derivations of the proposed architectures and digital hardware implementations are provided. All designs are implemented and tested on-chip using field programmable gate array (FPGA) technology and also simulated up to synthesis level for application specific integrated circuits (ASICs). Obtained accuracy and hardware metrics are presented and compared with the current state-of-the-art. Performance of AI based DCT computation algorithms in next generation video codecs are also analysed by integrating the proposed algorithms into high efficiency video coding standard (HEVC). The proposed digital architectures have potential applications in multimedia, automaticsurveillance, geospatial remote sensing, and automotive industry.","abstract_has_math":false,"creators":["Edirisuriya, Amila"],"institution":"University of Akron","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Madanayake, Arjuna"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013-05-21","date_published":"2013-05-21","updated_at":"2026-07-24T03:36:39Z","subjects":["Electrical Engineering","Computer Engineering","DCT","Algebraic integers","Digital architecture","FPGA","ASIC"],"languages":["English"],"rights":["unrestricted","This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws."],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://rave.ohiolink.edu/etdc/view?acc_num=akron1363233037","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Madanayake, Arjuna"]},{"key":"dc:creator","label":"Author","values":["Edirisuriya, Amila"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2013-05-21"]},{"key":"dc:publisher","label":"Institution","values":["University of Akron / OhioLINK"]},{"key":"dc:type","label":"Dc Type","values":["Electronic Thesis or Dissertation"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Akron"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrical Engineering","Computer Engineering","DCT","Algebraic integers","Digital architecture","FPGA","ASIC"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["English"]},{"key":"dc:rights","label":"Dc Rights","values":["unrestricted","This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws."]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://rave.ohiolink.edu/etdc/view?acc_num=akron1363233037"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The discrete cosine transform (DCT) is a key tool in many image and video coding applications. Therefore significant effort is been made to realize DCT computation utilizing minimum resources in terms of hardware, at acceptable accuracy. This thesis explores the use of number theoretic techniques such as algebraic integer (AI) encoding and expansion factor methods for exact and approximate DCT computation. Novel digital hardware architectures that utilize these techniques to obtain, a) improvements in accuracy b) reductions in area and power consumption, are proposed. Review of the utilized number theoretic techniques, mathematical derivations of the proposed architectures and digital hardware implementations are provided. All designs are implemented and tested on-chip using field programmable gate array (FPGA) technology and also simulated up to synthesis level for application specific integrated circuits (ASICs). Obtained accuracy and hardware metrics are presented and compared with the current state-of-the-art. Performance of AI based DCT computation algorithms in next generation video codecs are also analysed by integrating the proposed algorithms into high efficiency video coding standard (HEVC). The proposed digital architectures have potential applications in multimedia, automaticsurveillance, geospatial remote sensing, and automotive industry."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf","p.145","2.51 MB"]},{"key":"dc:title","label":"Title","values":["Digital Hardware Architectures for Exact and Approximate DCT Computation Using Number Theoretic Techniques"]}]}],"canonical_facts":{"dc:contributor":["Madanayake, Arjuna"],"dc:creator":["Edirisuriya, Amila"],"dc:date":["2013-05-21"],"dc:description":["The discrete cosine transform (DCT) is a key tool in many image and video coding applications. Therefore significant effort is been made to realize DCT computation utilizing minimum resources in terms of hardware, at acceptable accuracy. This thesis explores the use of number theoretic techniques such as algebraic integer (AI) encoding and expansion factor methods for exact and approximate DCT computation. Novel digital hardware architectures that utilize these techniques to obtain, a) improvements in accuracy b) reductions in area and power consumption, are proposed. Review of the utilized number theoretic techniques, mathematical derivations of the proposed architectures and digital hardware implementations are provided. All designs are implemented and tested on-chip using field programmable gate array (FPGA) technology and also simulated up to synthesis level for application specific integrated circuits (ASICs). Obtained accuracy and hardware metrics are presented and compared with the current state-of-the-art. Performance of AI based DCT computation algorithms in next generation video codecs are also analysed by integrating the proposed algorithms into high efficiency video coding standard (HEVC). The proposed digital architectures have potential applications in multimedia, automaticsurveillance, geospatial remote sensing, and automotive industry."],"dc:format":["application/pdf","p.145","2.51 MB"],"dc:identifier":["http://rave.ohiolink.edu/etdc/view?acc_num=akron1363233037"],"dc:language":["English"],"dc:publisher":["University of Akron / OhioLINK"],"dc:rights":["unrestricted","This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws."],"dc:subject":["Electrical Engineering","Computer Engineering","DCT","Algebraic integers","Digital architecture","FPGA","ASIC"],"dc:title":["Digital Hardware Architectures for Exact and Approximate DCT Computation Using Number Theoretic Techniques"],"dc:type":["Electronic Thesis or Dissertation"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["masters"],"thesis:degree_name":["Master of Science"],"thesis:institution_name":["University of Akron"]},"updated_at":"2026-07-24T03:36:39Z"}