PARALLEL ARCHITECTURES FOR REAL-TIME SAR RANGE-DOPPLER PROCESSING AND QUALITY AUTOMATIC FOCUSING ALGORITHM
type: CreativeWork
description: As part of an effort to develop a real-time Range-Doppler digital SAR processor, conceptual high-speed architecture designs for both the front-end video pre-filtering and systolic image formation are proposed. We named this HEMPSAR, which is the acronym for "Highly Efficient, Massively Parallel SAR processor. The SAR preprocessor is characterised by simultaneous DC bias cancellation and azimuth presurnming operations. The design consists of a single 3-D richly interconnected planes of novelly-adapted Modified Transverse FIR parallel tapped delay nodes. This architecture is best suited for ASIC implementation. On the other hand, the real-time SAR image formation processor is also designed with an architecture that emphasizes on properties of modularity, regularity, local interconnection so that parallel processing on low cost commercial massively processing nodes is possible. The architecture consists of a novel 3-D modified FIR filter that allows the incoming 2-D raw data samples to be convolved with the build-in 3-D array of reference data samples necessary for simultaneous range and azimuth compressions. Real-time SAR image focusing via an enhanced phase-gradient approach is also proposed. By selectively increasing the pool of synchronisation sources through utilization of more than 1 prominent scatterers per range gate, as well as with special target filtering procedure to final select these scatterers out of the large pool, the Quality Phase-Gradient Autofocus (QPGA) solution achieves near convergence quality without iteration. The focusing quality of QPGA has been shown to be better than the conventional PGA. Comparing in terms of computational speed (Pentium 200 platform), QPGA is 3 times faster than PGA for the same focusing quality. QPGA also has potential for better SAR map focusing performance even in the presence of moving target environment.
abstract: As part of an effort to develop a real-time Range-Doppler digital SAR processor, conceptual high-speed architecture designs for both the front-end video pre-filtering and systolic image formation are proposed. We named this HEMPSAR, which is the acronym for "Highly Efficient, Massively Parallel SAR processor. The SAR preprocessor is characterised by simultaneous DC bias cancellation and azimuth presurnming operations. The design consists of a single 3-D richly interconnected planes of novelly-adapted Modified Transverse FIR parallel tapped delay nodes. This architecture is best suited for ASIC implementation. On the other hand, the real-time SAR image formation processor is also designed with an architecture that emphasizes on properties of modularity, regularity, local interconnection so that parallel processing on low cost commercial massively processing nodes is possible. The architecture consists of a novel 3-D modified FIR filter that allows the incoming 2-D raw data samples to be convolved with the build-in 3-D array of reference data samples necessary for simultaneous range and azimuth compressions. Real-time SAR image focusing via an enhanced phase-gradient approach is also proposed. By selectively increasing the pool of synchronisation sources through utilization of more than 1 prominent scatterers per range gate, as well as with special target filtering procedure to final select these scatterers out of the large pool, the Quality Phase-Gradient Autofocus (QPGA) solution achieves near convergence quality without iteration. The focusing quality of QPGA has been shown to be better than the conventional PGA. Comparing in terms of computational speed (Pentium 200 platform), QPGA is 3 times faster than PGA for the same focusing quality. QPGA also has potential for better SAR map focusing performance even in the presence of moving target environment.
author: CHAN HIAN LIM
date published: 1997
date modified: 2026-07-24T03:31:38Z
provider: National University of Singapore
publisher: Networked Digital Library of Theses and Dissertations
type: WebPage
source organization: National University of Singapore