DESIGN OF A MULTI DSP SYSTEM FOR IMAGE PROCESSING

In this report the design and implementation of a multi digital signal processor (DSP) system for performing parallel image processing is described. Considering the characteristics of image problems and addressing their computation and communication needs, a data flow linear array pipeline communication network is chosen for the parallel architecture. This architecture is designed to supp01t computationally intensive applications that require movement of massive amount of data among processors as well as to exploit algorithmic parallelism and sequential data dependencies that is typical of image processing applications. High rate data flow is ensured through the use of a specially designed shared dual port dual access memory unit that sits in between two digital signal processors. The dual access memory unit consists of a few sub-modules being integrated together and is programmed by both digital signal processors to operate in one of its several operating modes. The dual p01t dual access DRAM bank is implemented using a dual access memory controller which forms the core control logic for the entire unit. The dual access memory unit combines shared memory with message passing for more efficient data transfer with sychronisation. This integration gives rise to a message based communication method that is advantageous and efficient in situations where there are known communication patterns such as in image processing. Messages are exchanged through the dual port SRAM with mailboxing capabilities and data exchange are carried out tlu·ough the dual access DRAM unit. In addition, the dual access memory controller has features that facilitate memory arbitration and OMA transfer capability. In order to exploit the parallelism of the system architecture, a programming model is proposed to maximize performance and efficiency. Issues addressed include program control and flow, data manipulation in blocks, programming for the message based communication and load balancing. Other designs to support the system include a high speed camera unit and a Downloader Unit. The camera unit acquires image data and is able to interleave access for the digital signal processor even before an entire image frame is captured. The Downloader Unit is designed to rapidly download program codes from the PC to the various digital signal processor modules.

Author dc:creator

• CHUA BENG HUAT