Structural Design and Optimization of 65nm Cu/low-k Flipchip Package

This paper describes the optimization of the structural design of Charteredb s C65 nm 21 mm x 21 mm die size FCBGA package incorporated with fully active and functional 9-metal Cu/ low-k layers and 150um interconnect pitch. The low-k material used in this study is non-porous SiCOH with a k value of 2.9. A parametric study using 2D plane strain finite element analysis was performed to study the effect of various parameters on the reliability of the large die package in order to arrive at an optimized design. In order to have a simple criteria to predict the reliability of the yet-to-be-built large die package, reliability tests were carried out on some existing 15 mm x 15 mm die Cu/low-k flip chip packages which were identical to the 21 mm x 21 mm die package except for the size. The packages were found to pass the reliability tests. 2D plane strain finite element analyses were then performed on the 15 mm x 15 mm die. The computed delamination stresses at the low-k layer and the strain energy density dissipation per cycle in the critical solder (W) were then used as a benchmark for the design of a larger flip chip package.

Author dc:creator

• ONG MENG GUAN, JIMMY

• Solder Joint Reliability, Finite Element Analysis, 65nm Cu/low-k, Large die, Flip Chip Package