{"id":{"repo_id":"nus","oai_identifier":"oai:scholarbank.nus.edu.sg:10635/153906"},"canonical_url":"https://search.dev.ndltd.org/etd/nus/oai:scholarbank.nus.edu.sg:10635/153906","repository":{"repo_id":"nus","name":"National University of Singapore","base_url":"https://scholarbank.nus.edu.sg/oai/request"},"display":{"title":"DESIGN, SIMULATION AND OPTIMIZATION OF HIGH Q RF SPIRAL INDUCTORS ON SILICON CHIPS","abstract":"In silicon-based radio-frequency integrated circuits, on-chip spiral inductors are widely used due to their low cost and ease of process integration. However, the lossy Si substrate makes the design of high Q passive components difficult. Although there have been many works done to find many methods to improve the Q factor, the optimization of the spiral inductors is a never end job, and there is a continually great incentive to design, optimize, and model spiral inductors fabricated on Si substrates. Our project firstly researches on the design and optimization of the spiral inductors with 6 µm Cu top layer based on the IME CMOS Cu interconnect technology. The effects of various structural and process parameters on the Q factor are explained in detail using the advanced electromagnetic simulator, HFSS, which shows the accurate simulation results and gives the guide for the on-chip inductors optimization. We finally find the optimal structure of n4w6s2t75th6 for the thick Cu inductors, which can improve the Q factor by 40% or so. The guide of optimizing 6 µm thick Cu spiral inductors is also given in detail in our project. At the meanwhile, we propose an equivalent circuit model, the advanced single-TT model using lumped RLC elements, to offer the physical insight of the planar inductors. Unlike the time-consuming 3-D simulator, the physical model can easily and quickly simulate the performance of the inductance L and the Q factor from the geometric structures of the inductors. The verification work has also been done to modify our scalable model with the measured results of various inductors.","abstract_html":"In silicon-based radio-frequency integrated circuits, on-chip spiral inductors are widely used due to their low cost and ease of process integration. However, the lossy Si substrate makes the design of high Q passive components difficult. Although there have been many works done to find many methods to improve the Q factor, the optimization of the spiral inductors is a never end job, and there is a continually great incentive to design, optimize, and model spiral inductors fabricated on Si substrates. Our project firstly researches on the design and optimization of the spiral inductors with 6 µm Cu top layer based on the IME CMOS Cu interconnect technology. The effects of various structural and process parameters on the Q factor are explained in detail using the advanced electromagnetic simulator, HFSS, which shows the accurate simulation results and gives the guide for the on-chip inductors optimization. We finally find the optimal structure of n4w6s2t75th6 for the thick Cu inductors, which can improve the Q factor by 40% or so. The guide of optimizing 6 µm thick Cu spiral inductors is also given in detail in our project. At the meanwhile, we propose an equivalent circuit model, the advanced single-TT model using lumped RLC elements, to offer the physical insight of the planar inductors. Unlike the time-consuming 3-D simulator, the physical model can easily and quickly simulate the performance of the inductance L and the Q factor from the geometric structures of the inductors. The verification work has also been done to modify our scalable model with the measured results of various inductors.","abstract_has_math":false,"creators":["LIN SHIWEI"],"institution":null,"degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2003,"date_issued":"2003","date_published":"2003","updated_at":"2026-07-24T03:33:34Z","subjects":["Quality factor","Spiral inductors","Structure design","Layout optimization","RF components","Inductor model","On-chip inductor"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":null,"outbound_label":null,"outbound_source":null},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["LIN SHIWEI"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.issued","label":"Date","values":["2003"]},{"key":"dc:relation.isreferencedby","label":"Dc Relation Isreferencedby","values":["https://scholarbank.nus.edu.sg/handle/10635/153906"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Quality factor","Spiral inductors","Structure design","Layout optimization","RF components","Inductor model","On-chip inductor"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://scholarbank.nus.edu.sg/bitstreams/cd2ce948-61e3-4db5-983a-0eb2effc80e2/download"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["In silicon-based radio-frequency integrated circuits, on-chip spiral inductors are widely used due to their low cost and ease of process integration. However, the lossy Si substrate makes the design of high Q passive components difficult. Although there have been many works done to find many methods to improve the Q factor, the optimization of the spiral inductors is a never end job, and there is a continually great incentive to design, optimize, and model spiral inductors fabricated on Si substrates. Our project firstly researches on the design and optimization of the spiral inductors with 6 µm Cu top layer based on the IME CMOS Cu interconnect technology. The effects of various structural and process parameters on the Q factor are explained in detail using the advanced electromagnetic simulator, HFSS, which shows the accurate simulation results and gives the guide for the on-chip inductors optimization. We finally find the optimal structure of n4w6s2t75th6 for the thick Cu inductors, which can improve the Q factor by 40% or so. The guide of optimizing 6 µm thick Cu spiral inductors is also given in detail in our project. At the meanwhile, we propose an equivalent circuit model, the advanced single-TT model using lumped RLC elements, to offer the physical insight of the planar inductors. Unlike the time-consuming 3-D simulator, the physical model can easily and quickly simulate the performance of the inductance L and the Q factor from the geometric structures of the inductors. The verification work has also been done to modify our scalable model with the measured results of various inductors."]},{"key":"dc:format.checksum.md5","label":"Dc Format Checksum Md5","values":["d7b1618b7b64223dcdf65af4b60a833d","d85aa8799ffa19ed3307285d0a8d88d1"]},{"key":"dc:title","label":"Title","values":["DESIGN, SIMULATION AND OPTIMIZATION OF HIGH Q RF SPIRAL INDUCTORS ON SILICON CHIPS"]}]}],"canonical_facts":{"dc:creator":["LIN SHIWEI"],"dc:date.issued":["2003"],"dc:description.abstract":["In silicon-based radio-frequency integrated circuits, on-chip spiral inductors are widely used due to their low cost and ease of process integration. However, the lossy Si substrate makes the design of high Q passive components difficult. Although there have been many works done to find many methods to improve the Q factor, the optimization of the spiral inductors is a never end job, and there is a continually great incentive to design, optimize, and model spiral inductors fabricated on Si substrates. Our project firstly researches on the design and optimization of the spiral inductors with 6 µm Cu top layer based on the IME CMOS Cu interconnect technology. The effects of various structural and process parameters on the Q factor are explained in detail using the advanced electromagnetic simulator, HFSS, which shows the accurate simulation results and gives the guide for the on-chip inductors optimization. We finally find the optimal structure of n4w6s2t75th6 for the thick Cu inductors, which can improve the Q factor by 40% or so. The guide of optimizing 6 µm thick Cu spiral inductors is also given in detail in our project. At the meanwhile, we propose an equivalent circuit model, the advanced single-TT model using lumped RLC elements, to offer the physical insight of the planar inductors. Unlike the time-consuming 3-D simulator, the physical model can easily and quickly simulate the performance of the inductance L and the Q factor from the geometric structures of the inductors. The verification work has also been done to modify our scalable model with the measured results of various inductors."],"dc:format.checksum.md5":["d7b1618b7b64223dcdf65af4b60a833d","d85aa8799ffa19ed3307285d0a8d88d1"],"dc:identifier.uri":["https://scholarbank.nus.edu.sg/bitstreams/cd2ce948-61e3-4db5-983a-0eb2effc80e2/download"],"dc:relation.isreferencedby":["https://scholarbank.nus.edu.sg/handle/10635/153906"],"dc:subject":["Quality factor","Spiral inductors","Structure design","Layout optimization","RF components","Inductor model","On-chip inductor"],"dc:title":["DESIGN, SIMULATION AND OPTIMIZATION OF HIGH Q RF SPIRAL INDUCTORS ON SILICON CHIPS"],"dc:type":["Thesis"]},"updated_at":"2026-07-24T03:33:34Z"}