Embedded machine vision - a parallel architecture approach -

Machine vision is one of the essential sensory functions in mobile robotics. To implement high performance vision processing, algorithms and hardware architectures must be well matched to exploit computational parallelism. Operations can be mapped into custom functional units to achieve higher performance compared to fixed processing units. Such approaches can eliminate the necessity of employing high-end processors. Firstly, an analytical mathematical model is proposed to estimate the required memory size and processing frequency. Next, custom architectures are designed with the considerations of optimising logic and memory resources. Specifically, the low pass filter, edge detection and thresholding algorithm are designed with the aim of processing a pixel within a single clock cycle. To achieve minimal usage of hardware resources, the redundant memory locations, logics and computations are removed. Lastly, simulation and hardware implementation are provided to demonstrate the performance of the embedded machine vision using FPGA.

Author dc:creator

• CHAN KIT WAI

• Embedded, Real-Time, Vision, Parallelism, Processor, FPGA