{"id":{"repo_id":"nps","oai_identifier":"oai:calhoun.nps.edu:10945/31533"},"canonical_url":"https://search.dev.ndltd.org/etd/nps/oai:calhoun.nps.edu:10945/31533","repository":{"repo_id":"nps","name":"Naval Postgraduate School","base_url":"https://calhoun.nps.edu/server/oai/request"},"display":{"title":"Optical SNS folding circuit design","abstract":"Recently, a new technique has been described for extending the resolution of an integrated optical multi-interferometer analog-to-digital converter (ADC). These types of ADCs can directly digitize the signals from an antenna and play an important role in eliminating the need for intermediate frequency and baseband processing. With resolution greater than 12 bits, these types of architectures are useful for a variety of applications. The new technique is based on the incorporation of a symmetrical number system (SNS) encoding to provide high resolution (greater than 1-bit per interferometer) while also reducing the complexity of the optical hardware. In this thesis the optical processor for an 8-bit folding ADC is designed. LabVIEW simulation of the interferometers is used to simultaneously allow for the testing of the digital circuit boards and the development of the optical front end of the ADC. Each component considered for the 8-bit optical design is discussed and the reason for the component selection is given. The 8-bit optical design is then documented and tested","abstract_html":"Recently, a new technique has been described for extending the resolution of an integrated optical multi-interferometer analog-to-digital converter (ADC). These types of ADCs can directly digitize the signals from an antenna and play an important role in eliminating the need for intermediate frequency and baseband processing. With resolution greater than 12 bits, these types of architectures are useful for a variety of applications. The new technique is based on the incorporation of a symmetrical number system (SNS) encoding to provide high resolution (greater than 1-bit per interferometer) while also reducing the complexity of the optical hardware. In this thesis the optical processor for an 8-bit folding ADC is designed. LabVIEW simulation of the interferometers is used to simultaneously allow for the testing of the digital circuit boards and the development of the optical front end of the ADC. Each component considered for the 8-bit optical design is discussed and the reason for the component selection is given. The 8-bit optical design is then documented and tested","abstract_has_math":false,"creators":["Crowe, Craig A."],"institution":"Monterey, California. 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The new technique is based on the incorporation of a symmetrical number system (SNS) encoding to provide high resolution (greater than 1-bit per interferometer) while also reducing the complexity of the optical hardware. In this thesis the optical processor for an 8-bit folding ADC is designed. LabVIEW simulation of the interferometers is used to simultaneously allow for the testing of the digital circuit boards and the development of the optical front end of the ADC. Each component considered for the 8-bit optical design is discussed and the reason for the component selection is given. The 8-bit optical design is then documented and tested"],"dc:identifier.uri":["https://hdl.handle.net/10945/31533"],"dc:language.iso":["en_US"],"dc:publisher":["Monterey, California. Naval Postgraduate School"],"dc:rights":["This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. 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