A design of floating point FFT using Genesil Silicon Compiler.

The hardware of floating-point MULTIPLY, ADD, and SUBTRACT units are designed to support the multiplication, addition, and subtraction operation necessary in the Fast Fourier Transform (FFT). In this thesis, the IEEE floating-point standard is adopted and scaled down to 16 bits, but the exponent is an excess-8 number represented using radix-2. A 16 bit reduced word size floating-point arithematic unit for high speed signal analysis was implemented. The layout verification, functional simulation, and timing analysis of these units have been performed on the Genesil Silicon Compiler (GSC) system that was developed to overcome the shortcomings of the time consuming custom layout methods. The design of this thesis work can be used for further investigation of the high speed, pipelined floating-point arithmetic units.

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Monterey, California. Naval Postgraduate School

Year dc:date.issued

1991

Author dc:creator

• Lu, Chung-Kuei.

Advisor dc:contributor.advisor

• Yang, Chyan

Statement dc:rights

• This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.

Language dc:language.iso

en_US

Handle dc:identifier.uri

https://hdl.handle.net/10945/30956

OAI identifier oai:identifier

oai:calhoun.nps.edu:10945/30956