{"id":{"repo_id":"njit","oai_identifier":"oai:digitalcommons.njit.edu:dissertations-1297"},"canonical_url":"https://search.dev.ndltd.org/etd/njit/oai:digitalcommons.njit.edu:dissertations-1297","repository":{"repo_id":"njit","name":"NJIT","base_url":"https://digitalcommons.njit.edu/do/oai/"},"display":{"title":"TiN/HfO2/SiO2/Si gate stacks reliability : Contribution of HfO2 and interfacial SiO2 layer","abstract":"Hafnium Oxide based gate stacks are considered to be the potential candidates to replace SiO_2 in complementary metal-oxide-semiconductor (CMOS), as they reduce the gate leakage by over 100 times while keeping the device performance intact. Even though considerable performance improvement has been achieved, reliability of high-[kappa] devices for the next generation of transistors (45nm and beyond) which has an interfacial layer (IL: typically SiO_2) between high-[kappa] and the substrate, needs to be investigated. To understand the breakdown mechanism of high-[kappa]/SiO_2 gate stack completely, it is important to study this multi-layer structure extensively. For example, (i) the role of SiO_2 interfacial layers and bulk high-[kappa] gate dielectrics without any interfacial layer can be investigated separately while maintaining same growth conditions; (ii) the evolution of breakdown process can be studied through stress induced leakage current (SILC); (iii) relationship of various degradation mechanisms such as negative bias temperature instability (NBTI) with that of the dielectric breakdown; and (iv) a fast evaluation process to estimate statistical breakdown distribution. In this dissertation a comparative study was conducted to investigate individual breakdown characteristics of high-[kappa]/IL (ISSG SiO_2)/metal gate stacks, in-situ steam generated (ISSG)-SiO_2 MOS structures and HfO_2-only metal-insulator-metal (MIM) capacitors. Experimental results indicate that after constant voltage stress (CVS) identical degradation for progressive breakdown and SILC were observed in high-[kappa]/IL and SiO_2-only MOS devices, but HfO_2-only MIM capacitors showed insignificant SILC and progressive breakdown until it went into hard breakdown. Based on the observed SILC behavior and charge-to-breakdown (QBD), it was inferred that interfacial layer initiates progressive breakdown of metal gate/high-[kappa] gate stacks at room temperature. From normalized SILC ([Delta]Jg/Jg0) at accelerated temperature and activation energy of the timeto- breakdown (TBD), it was observed that IL initiates the gate stack breakdown at higher temperatures as well. A quantitative agreement was observed for key parameters of NBTI and time dependent dielectric breakdown (TDDB) such as the activation energies of threshold voltage change and SILC. The quality and thickness variation of the IL causes similar degradation on both NBTI and TDDB indicating that mechanism of these two reliability issues are related due to creation of identical defect types in the IL. CVS was used to investigate the statistical distribution of TBD, defined as soft or first breakdown where small sample size was considered. As TBD followed Weibull distribution, large sample size was not required. Since the failure process in static random access memory (SRAM) is typically predicted by the realistic TDDB model based on gate leakage current (IFAIL) rather than the conventional first breakdown criterion, the relevant failure distributions at IFAIL are non-Weibull including the progressive breakdown (PBD) phase for high-[kappa]/metal gate dielectrics. A new methodology using hybrid two-stage stresses has been developed to study progressive breakdown phase further for high-[kappa] and SiO_2. It is demonstrated that VRS can be used effectively for quantitative reliability studies of progressive breakdown phase and final breakdown of high-[kappa] and other dielectric materials; thus it can replace the time-consuming CVS measurements as an efficient methodology and reduce the resources manufacturing cost.","abstract_html":"Hafnium Oxide based gate stacks are considered to be the potential candidates to replace SiO_2 in complementary metal-oxide-semiconductor (CMOS), as they reduce the gate leakage by over 100 times while keeping the device performance intact. Even though considerable performance improvement has been achieved, reliability of high-[kappa] devices for the next generation of transistors (45nm and beyond) which has an interfacial layer (IL: typically SiO_2) between high-[kappa] and the substrate, needs to be investigated. To understand the breakdown mechanism of high-[kappa]/SiO_2 gate stack completely, it is important to study this multi-layer structure extensively. For example, (i) the role of SiO_2 interfacial layers and bulk high-[kappa] gate dielectrics without any interfacial layer can be investigated separately while maintaining same growth conditions; (ii) the evolution of breakdown process can be studied through stress induced leakage current (SILC); (iii) relationship of various degradation mechanisms such as negative bias temperature instability (NBTI) with that of the dielectric breakdown; and (iv) a fast evaluation process to estimate statistical breakdown distribution. In this dissertation a comparative study was conducted to investigate individual breakdown characteristics of high-[kappa]/IL (ISSG SiO_2)/metal gate stacks, in-situ steam generated (ISSG)-SiO_2 MOS structures and HfO_2-only metal-insulator-metal (MIM) capacitors. Experimental results indicate that after constant voltage stress (CVS) identical degradation for progressive breakdown and SILC were observed in high-[kappa]/IL and SiO_2-only MOS devices, but HfO_2-only MIM capacitors showed insignificant SILC and progressive breakdown until it went into hard breakdown. Based on the observed SILC behavior and charge-to-breakdown (QBD), it was inferred that interfacial layer initiates progressive breakdown of metal gate/high-[kappa] gate stacks at room temperature. From normalized SILC ([Delta]Jg/Jg0) at accelerated temperature and activation energy of the timeto- breakdown (TBD), it was observed that IL initiates the gate stack breakdown at higher temperatures as well. A quantitative agreement was observed for key parameters of NBTI and time dependent dielectric breakdown (TDDB) such as the activation energies of threshold voltage change and SILC. The quality and thickness variation of the IL causes similar degradation on both NBTI and TDDB indicating that mechanism of these two reliability issues are related due to creation of identical defect types in the IL. CVS was used to investigate the statistical distribution of TBD, defined as soft or first breakdown where small sample size was considered. As TBD followed Weibull distribution, large sample size was not required. Since the failure process in static random access memory (SRAM) is typically predicted by the realistic TDDB model based on gate leakage current (IFAIL) rather than the conventional first breakdown criterion, the relevant failure distributions at IFAIL are non-Weibull including the progressive breakdown (PBD) phase for high-[kappa]/metal gate dielectrics. A new methodology using hybrid two-stage stresses has been developed to study progressive breakdown phase further for high-[kappa] and SiO_2. It is demonstrated that VRS can be used effectively for quantitative reliability studies of progressive breakdown phase and final breakdown of high-[kappa] and other dielectric materials; thus it can replace the time-consuming CVS measurements as an efficient methodology and reduce the resources manufacturing cost.","abstract_has_math":false,"creators":["Rahim, Nilufa"],"institution":null,"degree_name":"Doctor of Philosophy in Electrical Engineering - (Ph.D.)","degree_level":null,"degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":["Durgamadhab Misra","Haim Grebel","Leonid Tsybeskov"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-01-31T08:00:00Z","date_published":"2011-01-31T08:00:00Z","updated_at":"2026-07-24T03:22:07Z","subjects":["CMOS","Reliability","High-k gate stack","CVS","HfO2","VRS","Electrical and Electronics"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://digitalcommons.njit.edu/dissertations/242","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Durgamadhab Misra","Haim Grebel","Leonid Tsybeskov"]},{"key":"dc:creator","label":"Author","values":["Rahim, Nilufa"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:type","label":"Dc Type","values":["Dissertation"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Doctor of Philosophy in Electrical Engineering - (Ph.D.)"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["CMOS","Reliability","High-k gate stack","CVS","HfO2","VRS","Electrical and Electronics"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://digitalcommons.njit.edu/dissertations/242"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Hafnium Oxide based gate stacks are considered to be the potential candidates to replace SiO_2 in complementary metal-oxide-semiconductor (CMOS), as they reduce the gate leakage by over 100 times while keeping the device performance intact. Even though considerable performance improvement has been achieved, reliability of high-[kappa] devices for the next generation of transistors (45nm and beyond) which has an interfacial layer (IL: typically SiO_2) between high-[kappa] and the substrate, needs to be investigated. To understand the breakdown mechanism of high-[kappa]/SiO_2 gate stack completely, it is important to study this multi-layer structure extensively. For example, (i) the role of SiO_2 interfacial layers and bulk high-[kappa] gate dielectrics without any interfacial layer can be investigated separately while maintaining same growth conditions; (ii) the evolution of breakdown process can be studied through stress induced leakage current (SILC); (iii) relationship of various degradation mechanisms such as negative bias temperature instability (NBTI) with that of the dielectric breakdown; and (iv) a fast evaluation process to estimate statistical breakdown distribution. In this dissertation a comparative study was conducted to investigate individual breakdown characteristics of high-[kappa]/IL (ISSG SiO_2)/metal gate stacks, in-situ steam generated (ISSG)-SiO_2 MOS structures and HfO_2-only metal-insulator-metal (MIM) capacitors. Experimental results indicate that after constant voltage stress (CVS) identical degradation for progressive breakdown and SILC were observed in high-[kappa]/IL and SiO_2-only MOS devices, but HfO_2-only MIM capacitors showed insignificant SILC and progressive breakdown until it went into hard breakdown. Based on the observed SILC behavior and charge-to-breakdown (QBD), it was inferred that interfacial layer initiates progressive breakdown of metal gate/high-[kappa] gate stacks at room temperature. From normalized SILC ([Delta]Jg/Jg0) at accelerated temperature and activation energy of the timeto- breakdown (TBD), it was observed that IL initiates the gate stack breakdown at higher temperatures as well. A quantitative agreement was observed for key parameters of NBTI and time dependent dielectric breakdown (TDDB) such as the activation energies of threshold voltage change and SILC. The quality and thickness variation of the IL causes similar degradation on both NBTI and TDDB indicating that mechanism of these two reliability issues are related due to creation of identical defect types in the IL. CVS was used to investigate the statistical distribution of TBD, defined as soft or first breakdown where small sample size was considered. As TBD followed Weibull distribution, large sample size was not required. Since the failure process in static random access memory (SRAM) is typically predicted by the realistic TDDB model based on gate leakage current (IFAIL) rather than the conventional first breakdown criterion, the relevant failure distributions at IFAIL are non-Weibull including the progressive breakdown (PBD) phase for high-[kappa]/metal gate dielectrics. A new methodology using hybrid two-stage stresses has been developed to study progressive breakdown phase further for high-[kappa] and SiO_2. It is demonstrated that VRS can be used effectively for quantitative reliability studies of progressive breakdown phase and final breakdown of high-[kappa] and other dielectric materials; thus it can replace the time-consuming CVS measurements as an efficient methodology and reduce the resources manufacturing cost."]},{"key":"dc:title","label":"Title","values":["TiN/HfO2/SiO2/Si gate stacks reliability : Contribution of HfO2 and interfacial SiO2 layer"]}]}],"canonical_facts":{"dc:contributor":["Durgamadhab Misra","Haim Grebel","Leonid Tsybeskov"],"dc:creator":["Rahim, Nilufa"],"dc:description.abstract":["Hafnium Oxide based gate stacks are considered to be the potential candidates to replace SiO_2 in complementary metal-oxide-semiconductor (CMOS), as they reduce the gate leakage by over 100 times while keeping the device performance intact. Even though considerable performance improvement has been achieved, reliability of high-[kappa] devices for the next generation of transistors (45nm and beyond) which has an interfacial layer (IL: typically SiO_2) between high-[kappa] and the substrate, needs to be investigated. To understand the breakdown mechanism of high-[kappa]/SiO_2 gate stack completely, it is important to study this multi-layer structure extensively. For example, (i) the role of SiO_2 interfacial layers and bulk high-[kappa] gate dielectrics without any interfacial layer can be investigated separately while maintaining same growth conditions; (ii) the evolution of breakdown process can be studied through stress induced leakage current (SILC); (iii) relationship of various degradation mechanisms such as negative bias temperature instability (NBTI) with that of the dielectric breakdown; and (iv) a fast evaluation process to estimate statistical breakdown distribution. In this dissertation a comparative study was conducted to investigate individual breakdown characteristics of high-[kappa]/IL (ISSG SiO_2)/metal gate stacks, in-situ steam generated (ISSG)-SiO_2 MOS structures and HfO_2-only metal-insulator-metal (MIM) capacitors. Experimental results indicate that after constant voltage stress (CVS) identical degradation for progressive breakdown and SILC were observed in high-[kappa]/IL and SiO_2-only MOS devices, but HfO_2-only MIM capacitors showed insignificant SILC and progressive breakdown until it went into hard breakdown. Based on the observed SILC behavior and charge-to-breakdown (QBD), it was inferred that interfacial layer initiates progressive breakdown of metal gate/high-[kappa] gate stacks at room temperature. From normalized SILC ([Delta]Jg/Jg0) at accelerated temperature and activation energy of the timeto- breakdown (TBD), it was observed that IL initiates the gate stack breakdown at higher temperatures as well. A quantitative agreement was observed for key parameters of NBTI and time dependent dielectric breakdown (TDDB) such as the activation energies of threshold voltage change and SILC. The quality and thickness variation of the IL causes similar degradation on both NBTI and TDDB indicating that mechanism of these two reliability issues are related due to creation of identical defect types in the IL. CVS was used to investigate the statistical distribution of TBD, defined as soft or first breakdown where small sample size was considered. As TBD followed Weibull distribution, large sample size was not required. Since the failure process in static random access memory (SRAM) is typically predicted by the realistic TDDB model based on gate leakage current (IFAIL) rather than the conventional first breakdown criterion, the relevant failure distributions at IFAIL are non-Weibull including the progressive breakdown (PBD) phase for high-[kappa]/metal gate dielectrics. A new methodology using hybrid two-stage stresses has been developed to study progressive breakdown phase further for high-[kappa] and SiO_2. It is demonstrated that VRS can be used effectively for quantitative reliability studies of progressive breakdown phase and final breakdown of high-[kappa] and other dielectric materials; thus it can replace the time-consuming CVS measurements as an efficient methodology and reduce the resources manufacturing cost."],"dc:identifier":["https://digitalcommons.njit.edu/dissertations/242"],"dc:subject":["CMOS","Reliability","High-k gate stack","CVS","HfO2","VRS","Electrical and Electronics"],"dc:title":["TiN/HfO2/SiO2/Si gate stacks reliability : Contribution of HfO2 and interfacial SiO2 layer"],"dc:type":["Dissertation"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_name":["Doctor of Philosophy in Electrical Engineering - (Ph.D.)"]},"updated_at":"2026-07-24T03:22:07Z"}