”This dissertation describes the application of a multi-level, memory-based approach for building digital circuits. To reflect the alternative approach, the basic science is termed digital reasoning and the specific CorMem technology is based on recent patents. CMOS transistors are used in a non-traditional way for multi-level operations and memory manipulation. The combination of multi-level architectures and matrix algebra principles can create flexible, modular systems using standard fabrication methods and can avoid many of the limitations of other multi-valued logic approaches.
Quaternary, memory-based systems are developed to implement logic-gate-type functions, digital adder circuits, a complete arithmetic and logic unit (ALU), quaternary-to-binary and binary-to-quaternary circuits, and ALU control circuits. All of these implementations use driver and array architectures using CMOS TSMC 130 micron technology. The circuit layouts and functional simulations are given and are compared to binary circuits with comparable functionality. Experimental performance of a hardware AND chip is also demonstrated including excellent signal discrimination. The digital reasoning approach requires more chip area for basic logic gate functionality, but it grows increasingly efficient for more complex systems through hardware reuse. Potential quaternary advantages include fewer interconnections, lesser area requirements, and lower power consumption”--Abstract, page iii.
","abstract_html":"<p>”This dissertation describes the application of a multi-level, memory-based approach for building digital circuits. To reflect the alternative approach, the basic science is termed digital reasoning and the specific CorMem technology is based on recent patents. CMOS transistors are used in a non-traditional way for multi-level operations and memory manipulation. The combination of multi-level architectures and matrix algebra principles can create flexible, modular systems using standard fabrication methods and can avoid many of the limitations of other multi-valued logic approaches.</p><p>Quaternary, memory-based systems are developed to implement logic-gate-type functions, digital adder circuits, a complete arithmetic and logic unit (ALU), quaternary-to-binary and binary-to-quaternary circuits, and ALU control circuits. All of these implementations use driver and array architectures using CMOS TSMC 130 micron technology. The circuit layouts and functional simulations are given and are compared to binary circuits with comparable functionality. Experimental performance of a hardware AND chip is also demonstrated including excellent signal discrimination. The digital reasoning approach requires more chip area for basic logic gate functionality, but it grows increasingly efficient for more complex systems through hardware reuse. Potential quaternary advantages include fewer interconnections, lesser area requirements, and lower power consumption”--Abstract, page iii.</p>","abstract_has_math":false,"creators":["Dugganapally, Indira Priyadarshini"],"institution":"Missouri University of Science and Technology","degree_name":"Ph. D. in Computer Engineering","degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":null,"date_issued":"","date_published":null,"updated_at":"2026-07-24T03:18:09Z","subjects":["CMOS architecture","Digital reasoning","Memory-based","Multi-valued","Quaternary","Computer Engineering"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://scholarsmine.mst.edu/doctoral_dissertations/3090","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Dugganapally, Indira Priyadarshini"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:type","label":"Dc Type","values":["Dissertation - Open Access"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph. D. in Computer Engineering"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Missouri University of Science and Technology"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["CMOS architecture","Digital reasoning","Memory-based","Multi-valued","Quaternary","Computer Engineering"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://scholarsmine.mst.edu/doctoral_dissertations/3090"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["”This dissertation describes the application of a multi-level, memory-based approach for building digital circuits. To reflect the alternative approach, the basic science is termed digital reasoning and the specific CorMem technology is based on recent patents. CMOS transistors are used in a non-traditional way for multi-level operations and memory manipulation. The combination of multi-level architectures and matrix algebra principles can create flexible, modular systems using standard fabrication methods and can avoid many of the limitations of other multi-valued logic approaches.
Quaternary, memory-based systems are developed to implement logic-gate-type functions, digital adder circuits, a complete arithmetic and logic unit (ALU), quaternary-to-binary and binary-to-quaternary circuits, and ALU control circuits. All of these implementations use driver and array architectures using CMOS TSMC 130 micron technology. The circuit layouts and functional simulations are given and are compared to binary circuits with comparable functionality. Experimental performance of a hardware AND chip is also demonstrated including excellent signal discrimination. The digital reasoning approach requires more chip area for basic logic gate functionality, but it grows increasingly efficient for more complex systems through hardware reuse. Potential quaternary advantages include fewer interconnections, lesser area requirements, and lower power consumption”--Abstract, page iii.
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Quaternary, memory-based systems are developed to implement logic-gate-type functions, digital adder circuits, a complete arithmetic and logic unit (ALU), quaternary-to-binary and binary-to-quaternary circuits, and ALU control circuits. All of these implementations use driver and array architectures using CMOS TSMC 130 micron technology. The circuit layouts and functional simulations are given and are compared to binary circuits with comparable functionality. Experimental performance of a hardware AND chip is also demonstrated including excellent signal discrimination. The digital reasoning approach requires more chip area for basic logic gate functionality, but it grows increasingly efficient for more complex systems through hardware reuse. Potential quaternary advantages include fewer interconnections, lesser area requirements, and lower power consumption”--Abstract, page iii.
"],"dc:identifier":["https://scholarsmine.mst.edu/doctoral_dissertations/3090"],"dc:subject":["CMOS architecture","Digital reasoning","Memory-based","Multi-valued","Quaternary","Computer Engineering"],"dc:title":["CorMem digital reasoning architecture using CMOS Technology"],"dc:type":["Dissertation - Open Access"],"thesis:degree_name":["Ph. D. in Computer Engineering"],"thesis:institution_name":["Missouri University of Science and Technology"]},"updated_at":"2026-07-24T03:18:09Z"}