“The concept of partial elements with normalized potential coefficients is developed for general media. A circuit extraction approach based on a mixed-potential integral equation formulation (CEMPIE) is further developed based on partial elements with normalized potential coefficients, to include vertical discontinuities and losses into the first principles formulation. The approach is used for various DC power bus modeling. SMT decoupling capacitor placement is studied by modeling various capacitor locations, and local decoupling effect is quantified as a function of capacitor/IC spacing and power/ground layer separation. A general procedure to extract lumped circuit models for interconnects in multi-layer substrates is developed based on a partial element equivalent circuit type method, and a physics-based circuit prototype. This procedure is further used for via inductance estimation for a DC power bus in a multi-layer substrate. Closed-form expressions for via self inductance are then derived as a function of power plane dimensions, via diameter, power/ground layer separation, and via location. The expressions can be used in practical designs for evaluating via inductance without the necessity of full-wave modeling, and, predicting power bus impedance as well as effective frequency range of decoupling capacitors”--Abstract, page iii.
","abstract_html":"<p>“The concept of partial elements with normalized potential coefficients is developed for general media. A circuit extraction approach based on a mixed-potential integral equation formulation (CEMPIE) is further developed based on partial elements with normalized potential coefficients, to include vertical discontinuities and losses into the first principles formulation. The approach is used for various DC power bus modeling. SMT decoupling capacitor placement is studied by modeling various capacitor locations, and local decoupling effect is quantified as a function of capacitor/IC spacing and power/ground layer separation. A general procedure to extract lumped circuit models for interconnects in multi-layer substrates is developed based on a partial element equivalent circuit type method, and a physics-based circuit prototype. This procedure is further used for via inductance estimation for a DC power bus in a multi-layer substrate. Closed-form expressions for via self inductance are then derived as a function of power plane dimensions, via diameter, power/ground layer separation, and via location. The expressions can be used in practical designs for evaluating via inductance without the necessity of full-wave modeling, and, predicting power bus impedance as well as effective frequency range of decoupling capacitors”--Abstract, page iii. </p>","abstract_has_math":false,"creators":["Fan, Jun"],"institution":"University of Missouri--Rolla","degree_name":"Ph. D. in Electrical Engineering","degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2016,"date_issued":"2016-02-10T08:00:00Z","date_published":"2016-02-10T08:00:00Z","updated_at":"2026-07-24T03:19:12Z","subjects":["Electrical and Computer Engineering"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://scholarsmine.mst.edu/doctoral_dissertations/1375","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Fan, Jun"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.available","label":"Dc Date Available","values":["2016-02-10T08:00:00Z"]},{"key":"dc:type","label":"Dc Type","values":["Dissertation - Restricted Access"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph. D. in Electrical Engineering"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Missouri--Rolla"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrical and Computer Engineering"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://scholarsmine.mst.edu/doctoral_dissertations/1375"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["“The concept of partial elements with normalized potential coefficients is developed for general media. A circuit extraction approach based on a mixed-potential integral equation formulation (CEMPIE) is further developed based on partial elements with normalized potential coefficients, to include vertical discontinuities and losses into the first principles formulation. The approach is used for various DC power bus modeling. SMT decoupling capacitor placement is studied by modeling various capacitor locations, and local decoupling effect is quantified as a function of capacitor/IC spacing and power/ground layer separation. A general procedure to extract lumped circuit models for interconnects in multi-layer substrates is developed based on a partial element equivalent circuit type method, and a physics-based circuit prototype. This procedure is further used for via inductance estimation for a DC power bus in a multi-layer substrate. Closed-form expressions for via self inductance are then derived as a function of power plane dimensions, via diameter, power/ground layer separation, and via location. The expressions can be used in practical designs for evaluating via inductance without the necessity of full-wave modeling, and, predicting power bus impedance as well as effective frequency range of decoupling capacitors”--Abstract, page iii.
"]},{"key":"dc:title","label":"Title","values":["Modeling and design of DC power buses in high-speed digital circuit designs"]}]}],"canonical_facts":{"dc:creator":["Fan, Jun"],"dc:date.available":["2016-02-10T08:00:00Z"],"dc:description.abstract":["“The concept of partial elements with normalized potential coefficients is developed for general media. A circuit extraction approach based on a mixed-potential integral equation formulation (CEMPIE) is further developed based on partial elements with normalized potential coefficients, to include vertical discontinuities and losses into the first principles formulation. The approach is used for various DC power bus modeling. SMT decoupling capacitor placement is studied by modeling various capacitor locations, and local decoupling effect is quantified as a function of capacitor/IC spacing and power/ground layer separation. A general procedure to extract lumped circuit models for interconnects in multi-layer substrates is developed based on a partial element equivalent circuit type method, and a physics-based circuit prototype. This procedure is further used for via inductance estimation for a DC power bus in a multi-layer substrate. Closed-form expressions for via self inductance are then derived as a function of power plane dimensions, via diameter, power/ground layer separation, and via location. The expressions can be used in practical designs for evaluating via inductance without the necessity of full-wave modeling, and, predicting power bus impedance as well as effective frequency range of decoupling capacitors”--Abstract, page iii.
"],"dc:identifier":["https://scholarsmine.mst.edu/doctoral_dissertations/1375"],"dc:subject":["Electrical and Computer Engineering"],"dc:title":["Modeling and design of DC power buses in high-speed digital circuit designs"],"dc:type":["Dissertation - Restricted Access"],"thesis:degree_name":["Ph. D. in Electrical Engineering"],"thesis:institution_name":["University of Missouri--Rolla"]},"updated_at":"2026-07-24T03:19:12Z"}