Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms

Shao, Jun

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Michigan Technological University

Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms

dc:creator Shao, Jun

thesis:degree_name Doctor of Philosophy in Electrical Engineering (PhD)

Degree

thesis:*

Name thesis:degree_name: Doctor of Philosophy in Electrical Engineering (PhD)
Level thesis:degree_level: Dissertation

Author and committee

dc:creator, dc:contributor.*

Author dc:creator: Shao, Jun
Contributors dc:contributor: Brian Thomas Davis

Subjects

dc:subject × 2

Identifiers

dc:identifier.*

Identifier: https://digitalcommons.mtu.edu/etds/72
OAI identifier oai:identifier: oai:digitalcommons.mtu.edu:etds-1071

Chain of custody

source

Harvested from: Michigan Technological University
Base URL: digitalcommons.mtu.edu/do/oai/
Last updated: 2026-07-27
Source record: OAI-PMH GetRecord

related terms

citation

Shao, Jun. Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms. Dissertation thesis, https://doi.org/10.37099/mtu.dc.etds/72

Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms

Degree

Author and committee

Subjects

Identifiers

Chain of custody

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