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Massachusetts Institute of Technology

Production lead time reduction in a semiconductor capital equipment manufacturing plant through optimized testing protocols

Abstract

dc:description.abstract

Processes at a semiconductor equipment manufacturing facility were studied with the goal to reduce the production lead time. Based on the principles of lean manufacturing, DMAIC methodology was used to guide the process. Value Stream Mapping (VSM) of the whole process was done to determine that the Universal End Station (UES) was the module with the longest lead time. This work focuses on the optimization of the testing process on the UES. Time studies were conducted for the assembly and test of the UES module and analysis of results revealed a testing process that is serial and thus of a very long duration. Further investigations revealed that some of the processes required the test technician to do manual calibrations and measurements which resulted in long test times. Based on the interviews with involved personnel, historical data analysis and the research carried out, specific tests were recommended for automated testing and parallel testing. A decision tree was developed to help aid in the selection of the suitable candidates for automation while a dependency network diagram was developed to aid in selection of candidates for parallel testing. It is projected that these recommendations will reduce the Testing lead time of UES by 8.4% and labor hours by 16.3%. Keywords: Lean manufacturing, semiconductor, optimization, bottle neck, lead time, DMAIC, Value Stream Mapping, Time study, Root cause analysis.

Degree

thesis:*
Department dc:contributor.department
Massachusetts Institute of Technology. Department of Mechanical Engineering.
Grantor dc:publisher
Massachusetts Institute of Technology
Year dc:date.issued
2014

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Bhadauria, Anubha Singh
Advisor dc:contributor.advisor
  • Stephen C. Graves.

Subjects

dc:subject × 1

Rights

dc:rights
Statement dc:rights
  • M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
Language dc:language.iso
eng

Identifiers

dc:identifier.*
Handle dc:identifier.uri
http://hdl.handle.net/1721.1/93841
OAI identifier oai:identifier
oai:dspace.mit.edu:1721.1/93841

Chain of custody

source
Harvested from
MIT
Base URL
dspace.mit.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Bhadauria, Anubha Singh. Production lead time reduction in a semiconductor capital equipment manufacturing plant through optimized testing protocols. Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/93841