Building blocks of a 250MHz bandwidth, 10-bit continuous-time delta-sigma analog to digital converter

This thesis examines the design of a continuous time Delta-Sigma Analog to Digital Converter with the target performance to be 10-bit, 250MHz bandwidth with 200mW power dissipation.The design process involves choosing a top-level architecture and designing transistor-level blocks. The architecture is selected to be second-order, 3-bit with a 32 oversampling rate based on the ideal model simulation in MATLAB. The transistor-level circuits are designed in a BiCMOS technology. The SQNR result is 63.3dB and the power is 140mW.

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2014

Advisor dc:contributor.advisor

• Charles G. Sodini and Benjamin Walker.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/91886

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/91886