A 16-bit, 100kS/s self-calibrating cyclic analog-to-digital converter

Self-calibrating AID architectures minimize the sometimes expensive process of in-factory calibration, thus allowing manufacturers to reduce chip cost. This thesis presents an AID converter built using one such architecture, the reference-refreshing architecture. This converter shows under simulation 100 kHz performance at 16 bits, with INL of 1.2 LSBs, SNR of 89 dB, and power consumption of 170 mW.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2000

Author dc:creator

• Guidry, Michael J. (Michael James), 1976-

Advisor dc:contributor.advisor

• Hae-Seung Lee.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/9075

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/9075