{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/87918"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/87918","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Optical receiver techniques for integrated photonic links","abstract":"Integrated photonics has emerged as an I/O technology set to disrupt the communication fabric of many-core computer systems. The optical technology uses wavelength-division-multiplexing and a high degree of integration in order to surpass electrical I/O in both throughput and energy by more than an order of magnitude. However, integrated photonic systems need to be properly designed in order to reach their full potential, and electronic design techniques need to be updated to take full advantage of tight integration with photonics. This thesis explores the engineering of integrated photonics systems, focusing on optical data receiver design and techniques. We develop a representation of a photonic communication system based on circuit and device models, and perform a system-level optimization to find the optimal operating point for each of the components. This operating point sets the specification for the receiver circuits developed. An equivalent model of the receiver is used to develop a host of split-photodiode topologies that enable new ways to implement double-data-rate and decision-feedback-equalization operation. The receivers are fabricated as part of an integrated photonic test platform, and the measurements are detailed. This work presents the first-ever monolithically-integrated optical receiver with pA-sensitivity in a zero-foundry-change, commercial SOI CMOS logic process, and the first-ever monolithically-integrated optical receiver in a bulk CMOS memory process as part of a 9x5Gb/s DWDM receiver bank.","abstract_html":"Integrated photonics has emerged as an I/O technology set to disrupt the communication fabric of many-core computer systems. The optical technology uses wavelength-division-multiplexing and a high degree of integration in order to surpass electrical I/O in both throughput and energy by more than an order of magnitude. However, integrated photonic systems need to be properly designed in order to reach their full potential, and electronic design techniques need to be updated to take full advantage of tight integration with photonics. This thesis explores the engineering of integrated photonics systems, focusing on optical data receiver design and techniques. We develop a representation of a photonic communication system based on circuit and device models, and perform a system-level optimization to find the optimal operating point for each of the components. This operating point sets the specification for the receiver circuits developed. An equivalent model of the receiver is used to develop a host of split-photodiode topologies that enable new ways to implement double-data-rate and decision-feedback-equalization operation. The receivers are fabricated as part of an integrated photonic test platform, and the measurements are detailed. This work presents the first-ever monolithically-integrated optical receiver with pA-sensitivity in a zero-foundry-change, commercial SOI CMOS logic process, and the first-ever monolithically-integrated optical receiver in a bulk CMOS memory process as part of a 9x5Gb/s DWDM receiver bank.","abstract_has_math":false,"creators":["Georgas, Michael S. (Michael Stephen)"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Vladimir Stojanović."],"committee_chairs":[],"committee_members":[],"year":2014,"date_issued":"2014","date_published":"2014","updated_at":"2026-07-22T22:22:20Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/87918","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Vladimir Stojanović."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."]},{"key":"dc:contributor.other","label":"Dc Contributor Other","values":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."]},{"key":"dc:creator","label":"Author","values":["Georgas, Michael S. (Michael Stephen)"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-06-13T22:32:07Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-06-13T22:32:07Z"]},{"key":"dc:date.issued","label":"Date","values":["2014"]},{"key":"dc:publisher","label":"Institution","values":["Massachusetts Institute of Technology"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrical Engineering and Computer Science."]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://dspace.mit.edu/handle/1721.1/7582"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1721.1/87918"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.","Cataloged from PDF version of thesis.","Includes bibliographical references (pages 125-129)."]},{"key":"dc:description.abstract","label":"Abstract","values":["Integrated photonics has emerged as an I/O technology set to disrupt the communication fabric of many-core computer systems. The optical technology uses wavelength-division-multiplexing and a high degree of integration in order to surpass electrical I/O in both throughput and energy by more than an order of magnitude. However, integrated photonic systems need to be properly designed in order to reach their full potential, and electronic design techniques need to be updated to take full advantage of tight integration with photonics. This thesis explores the engineering of integrated photonics systems, focusing on optical data receiver design and techniques. We develop a representation of a photonic communication system based on circuit and device models, and perform a system-level optimization to find the optimal operating point for each of the components. This operating point sets the specification for the receiver circuits developed. An equivalent model of the receiver is used to develop a host of split-photodiode topologies that enable new ways to implement double-data-rate and decision-feedback-equalization operation. The receivers are fabricated as part of an integrated photonic test platform, and the measurements are detailed. This work presents the first-ever monolithically-integrated optical receiver with pA-sensitivity in a zero-foundry-change, commercial SOI CMOS logic process, and the first-ever monolithically-integrated optical receiver in a bulk CMOS memory process as part of a 9x5Gb/s DWDM receiver bank."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Ph. D."]},{"key":"dc:title","label":"Title","values":["Optical receiver techniques for integrated photonic links"]}]}],"canonical_facts":{"dc:contributor.advisor":["Vladimir Stojanović."],"dc:contributor.department":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."],"dc:contributor.other":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."],"dc:creator":["Georgas, Michael S. (Michael Stephen)"],"dc:date.accessioned":["2014-06-13T22:32:07Z"],"dc:date.available":["2014-06-13T22:32:07Z"],"dc:date.issued":["2014"],"dc:description":["Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.","Cataloged from PDF version of thesis.","Includes bibliographical references (pages 125-129)."],"dc:description.abstract":["Integrated photonics has emerged as an I/O technology set to disrupt the communication fabric of many-core computer systems. The optical technology uses wavelength-division-multiplexing and a high degree of integration in order to surpass electrical I/O in both throughput and energy by more than an order of magnitude. However, integrated photonic systems need to be properly designed in order to reach their full potential, and electronic design techniques need to be updated to take full advantage of tight integration with photonics. This thesis explores the engineering of integrated photonics systems, focusing on optical data receiver design and techniques. We develop a representation of a photonic communication system based on circuit and device models, and perform a system-level optimization to find the optimal operating point for each of the components. This operating point sets the specification for the receiver circuits developed. An equivalent model of the receiver is used to develop a host of split-photodiode topologies that enable new ways to implement double-data-rate and decision-feedback-equalization operation. The receivers are fabricated as part of an integrated photonic test platform, and the measurements are detailed. This work presents the first-ever monolithically-integrated optical receiver with pA-sensitivity in a zero-foundry-change, commercial SOI CMOS logic process, and the first-ever monolithically-integrated optical receiver in a bulk CMOS memory process as part of a 9x5Gb/s DWDM receiver bank."],"dc:description.degree":["Ph. D."],"dc:identifier.uri":["http://hdl.handle.net/1721.1/87918"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Electrical Engineering and Computer Science."],"dc:title":["Optical receiver techniques for integrated photonic links"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:22:20Z"}