Design and fabrication of an RF power LDMOSFET on SOI

This thesis studied thin-film Silicon-on-Insulator (SOI) LDMOSFET technology for RF power amplifier applications. To conduct this study, two generations of SOI RF power devices for portable wireless systems were designed and fabricated. Bulk silicon LDMOSFETs were also made and used as a bench-mark for comparison with the SOI LDMOSFETs. A metal/polysilicon damascene gate process was developed to reduce the gate resistance and achieve high RF power gain. The advantages and disadvantages of SOI for RF power applications were analyzed using these devices. This research showed that the primary advantage of SOI in RF power applications was the reduction of RF substrate loss due to the presence of the buried oxide. SOI was shown to reduce both drain substrate loss and pad substrate loss. Both contributed to an improvement in the device's power efficiency. An improvement of 5 percentage points of efficiency was demonstrated relative to bulk LDMOSFETs at 1.9 GHz. The SOI devices achieved excellent performance: over 62 % PAE at 1.9 GHz with 200 mW of output power at a Vdd of 3.6 V.

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2002

Author dc:creator

• Fiorenza, James G. (James George), 1972-

Advisor dc:contributor.advisor

• Jesús A. del Alamo.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/87329

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/87329