{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/86775"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/86775","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Oversampled pipline A/D converters with mismatch shaping","abstract":"This thesis introduces a technique to improve the linearity of pipeline analog to digital converters (ADC). Through a combination of oversampling and mismatch shaping, the distortion introduced by component mismatch is modulated out of the input signal frequency band, where it can be removed by subsequent digital filters, significantly improving the linearity. Mismatch shaping can be realized in traditional 1-bit-per-stage pipeline ADCs, but suffers from some fundamental limitations, which limit its effectiveness at pushing the distortion out of band. These limitations can be alleviated by using a 1 bit/stage commutative feedback capacitor switching (CFCS) pipeline design, due to the properties of the CFCS ADC's transfer characteristic, which has reduced differential nonlinearity (DNL) and an even integral nonlinearity (INL). The CFCS converter offers the foundation for the implementation of many different algorithms for mismatch shaping, some with very simple circuit realizations. It is possible to generalize some of these ideas to multi-bit-per-stage pipelines, but with reduced effectiveness. A test-chip was fabricated in a 0.35[mu]m CMOS process to demonstrate mismatch shaping in a 1-bit-per-stage CFCS pipeline ADC. The experimental results obtained from this chip indicate that the Spurious Free Dynamic Range (SFDR) improves by 8.5dB to 76dB when mismatch shaping is used at an oversampling ratio of 4 and a sampling rate of 61MHz. The Signal to Noise and Distortion Ratio (SNDR) improves by 3dB and the maximum Integral Nonlinearity (INL) decreases from 1.8LSB to 0.6LSB at the 12-bit level.","abstract_html":"This thesis introduces a technique to improve the linearity of pipeline analog to digital converters (ADC). Through a combination of oversampling and mismatch shaping, the distortion introduced by component mismatch is modulated out of the input signal frequency band, where it can be removed by subsequent digital filters, significantly improving the linearity. Mismatch shaping can be realized in traditional 1-bit-per-stage pipeline ADCs, but suffers from some fundamental limitations, which limit its effectiveness at pushing the distortion out of band. These limitations can be alleviated by using a 1 bit/stage commutative feedback capacitor switching (CFCS) pipeline design, due to the properties of the CFCS ADC's transfer characteristic, which has reduced differential nonlinearity (DNL) and an even integral nonlinearity (INL). The CFCS converter offers the foundation for the implementation of many different algorithms for mismatch shaping, some with very simple circuit realizations. It is possible to generalize some of these ideas to multi-bit-per-stage pipelines, but with reduced effectiveness. A test-chip was fabricated in a 0.35[mu]m CMOS process to demonstrate mismatch shaping in a 1-bit-per-stage CFCS pipeline ADC. The experimental results obtained from this chip indicate that the Spurious Free Dynamic Range (SFDR) improves by 8.5dB to 76dB when mismatch shaping is used at an oversampling ratio of 4 and a sampling rate of 61MHz. The Signal to Noise and Distortion Ratio (SNDR) improves by 3dB and the maximum Integral Nonlinearity (INL) decreases from 1.8LSB to 0.6LSB at the 12-bit level.","abstract_has_math":false,"creators":["Shabra, Ayman U. (Ayman Umar)"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Hae-Seung Lee."],"committee_chairs":[],"committee_members":[],"year":2001,"date_issued":"2001","date_published":"2001","updated_at":"2026-07-22T22:22:31Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/86775","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Hae-Seung Lee."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."]},{"key":"dc:contributor.other","label":"Dc Contributor Other","values":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."]},{"key":"dc:creator","label":"Author","values":["Shabra, Ayman U. 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Through a combination of oversampling and mismatch shaping, the distortion introduced by component mismatch is modulated out of the input signal frequency band, where it can be removed by subsequent digital filters, significantly improving the linearity. Mismatch shaping can be realized in traditional 1-bit-per-stage pipeline ADCs, but suffers from some fundamental limitations, which limit its effectiveness at pushing the distortion out of band. These limitations can be alleviated by using a 1 bit/stage commutative feedback capacitor switching (CFCS) pipeline design, due to the properties of the CFCS ADC's transfer characteristic, which has reduced differential nonlinearity (DNL) and an even integral nonlinearity (INL). The CFCS converter offers the foundation for the implementation of many different algorithms for mismatch shaping, some with very simple circuit realizations. It is possible to generalize some of these ideas to multi-bit-per-stage pipelines, but with reduced effectiveness. A test-chip was fabricated in a 0.35[mu]m CMOS process to demonstrate mismatch shaping in a 1-bit-per-stage CFCS pipeline ADC. The experimental results obtained from this chip indicate that the Spurious Free Dynamic Range (SFDR) improves by 8.5dB to 76dB when mismatch shaping is used at an oversampling ratio of 4 and a sampling rate of 61MHz. The Signal to Noise and Distortion Ratio (SNDR) improves by 3dB and the maximum Integral Nonlinearity (INL) decreases from 1.8LSB to 0.6LSB at the 12-bit level."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Ph.D."]},{"key":"dc:title","label":"Title","values":["Oversampled pipline A/D converters with mismatch shaping"]}]}],"canonical_facts":{"dc:contributor.advisor":["Hae-Seung Lee."],"dc:contributor.department":["Massachusetts Institute of Technology. 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Mismatch shaping can be realized in traditional 1-bit-per-stage pipeline ADCs, but suffers from some fundamental limitations, which limit its effectiveness at pushing the distortion out of band. These limitations can be alleviated by using a 1 bit/stage commutative feedback capacitor switching (CFCS) pipeline design, due to the properties of the CFCS ADC's transfer characteristic, which has reduced differential nonlinearity (DNL) and an even integral nonlinearity (INL). The CFCS converter offers the foundation for the implementation of many different algorithms for mismatch shaping, some with very simple circuit realizations. It is possible to generalize some of these ideas to multi-bit-per-stage pipelines, but with reduced effectiveness. A test-chip was fabricated in a 0.35[mu]m CMOS process to demonstrate mismatch shaping in a 1-bit-per-stage CFCS pipeline ADC. The experimental results obtained from this chip indicate that the Spurious Free Dynamic Range (SFDR) improves by 8.5dB to 76dB when mismatch shaping is used at an oversampling ratio of 4 and a sampling rate of 61MHz. The Signal to Noise and Distortion Ratio (SNDR) improves by 3dB and the maximum Integral Nonlinearity (INL) decreases from 1.8LSB to 0.6LSB at the 12-bit level."],"dc:description.degree":["Ph.D."],"dc:identifier.uri":["http://hdl.handle.net/1721.1/86775"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. 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