{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/84886"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/84886","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Miniaturized, low-voltage power converters with fast dynamic response","abstract":"This thesis introduces a two-stage architecture that combines the strengths of switched capacitor (SC) techniques (small size, light-load performance) with the high efficiency and regulation capability of switch-mode power converters. The resulting designs have a superior efficient-power density trade-off over traditional designs. These power converters can provide numerous lowvoltage outputs over a wide input voltage range with a very fast dynamic response, which are ideal for powering logic devices in the mobile and high-performance computing markets. Both design and fabrication considerations for power converters using this architecture are addressed. The results are demonstrated in a 2.4 W dc-dc converter implemented in a 180 nm CMOS IC process and co-packaged with its passive components for high-performance. The converter operates from an input voltage of 2.7 V to 5.5 V with an output voltage of </= 1.2 V, and achieves a 2210 W/inch³ power density with >/= 80% efficiency.","abstract_html":"This thesis introduces a two-stage architecture that combines the strengths of switched capacitor (SC) techniques (small size, light-load performance) with the high efficiency and regulation capability of switch-mode power converters. The resulting designs have a superior efficient-power density trade-off over traditional designs. These power converters can provide numerous lowvoltage outputs over a wide input voltage range with a very fast dynamic response, which are ideal for powering logic devices in the mobile and high-performance computing markets. Both design and fabrication considerations for power converters using this architecture are addressed. The results are demonstrated in a 2.4 W dc-dc converter implemented in a 180 nm CMOS IC process and co-packaged with its passive components for high-performance. The converter operates from an input voltage of 2.7 V to 5.5 V with an output voltage of &lt;/= 1.2 V, and achieves a 2210 W/inch³ power density with &gt;/= 80% efficiency.","abstract_has_math":false,"creators":["Giuliano, David (David Michael)"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["David J. Perreault."],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013","date_published":"2013","updated_at":"2026-07-22T22:21:40Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/84886","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["David J. 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The results are demonstrated in a 2.4 W dc-dc converter implemented in a 180 nm CMOS IC process and co-packaged with its passive components for high-performance. The converter operates from an input voltage of 2.7 V to 5.5 V with an output voltage of </= 1.2 V, and achieves a 2210 W/inch³ power density with >/= 80% efficiency."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Ph.D."]},{"key":"dc:title","label":"Title","values":["Miniaturized, low-voltage power converters with fast dynamic response"]}]}],"canonical_facts":{"dc:contributor.advisor":["David J. Perreault."],"dc:contributor.department":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."],"dc:contributor.other":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."],"dc:creator":["Giuliano, David (David Michael)"],"dc:date.accessioned":["2014-02-10T16:58:36Z"],"dc:date.available":["2014-02-10T16:58:36Z"],"dc:date.issued":["2013"],"dc:description":["Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.","Cataloged from PDF version of thesis.","Includes bibliographical references (pages 216-224)."],"dc:description.abstract":["This thesis introduces a two-stage architecture that combines the strengths of switched capacitor (SC) techniques (small size, light-load performance) with the high efficiency and regulation capability of switch-mode power converters. The resulting designs have a superior efficient-power density trade-off over traditional designs. These power converters can provide numerous lowvoltage outputs over a wide input voltage range with a very fast dynamic response, which are ideal for powering logic devices in the mobile and high-performance computing markets. Both design and fabrication considerations for power converters using this architecture are addressed. The results are demonstrated in a 2.4 W dc-dc converter implemented in a 180 nm CMOS IC process and co-packaged with its passive components for high-performance. The converter operates from an input voltage of 2.7 V to 5.5 V with an output voltage of </= 1.2 V, and achieves a 2210 W/inch³ power density with >/= 80% efficiency."],"dc:description.degree":["Ph.D."],"dc:identifier.uri":["http://hdl.handle.net/1721.1/84886"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. 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