{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/84855"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/84855","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Low-energy radix-2 serial and parallel FFT designs","abstract":"The push for portable electronics for communication and biomedical applications has accelerated the growing momentum for high performance and low energy hardware implementations of the Fast Fourier Transform (FFT). This work presents several new hardware implementations of the radix-2 FFT algorithms that take advantage of intermittent data and parallelism to reduce the energy per FFT. In the modified serial design, by using a low-power control memory and a pipelined data look-ahead controller to optimize processing of sequences of data with zeros, up to 45% of energy savings are achieved as compared to the baseline design. Two fully parallel FFTs with different datapaths are also developed based on a FFT flow diagram with the same geometry in each stage. Energy savings of up to 90% (an order of magnitude) are achieved as compared to the baseline design. These results are demonstrated through post-layout and parasitic extraction Nanosim simulations with 90nm standard cell libraries.","abstract_html":"The push for portable electronics for communication and biomedical applications has accelerated the growing momentum for high performance and low energy hardware implementations of the Fast Fourier Transform (FFT). This work presents several new hardware implementations of the radix-2 FFT algorithms that take advantage of intermittent data and parallelism to reduce the energy per FFT. In the modified serial design, by using a low-power control memory and a pipelined data look-ahead controller to optimize processing of sequences of data with zeros, up to 45% of energy savings are achieved as compared to the baseline design. Two fully parallel FFTs with different datapaths are also developed based on a FFT flow diagram with the same geometry in each stage. Energy savings of up to 90% (an order of magnitude) are achieved as compared to the baseline design. These results are demonstrated through post-layout and parasitic extraction Nanosim simulations with 90nm standard cell libraries.","abstract_has_math":false,"creators":["Zhang, DongNi"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Anantha P. Chandrakasan."],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013","date_published":"2013","updated_at":"2026-07-22T22:22:29Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/84855","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Anantha P. Chandrakasan."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."]},{"key":"dc:contributor.other","label":"Dc Contributor Other","values":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."]},{"key":"dc:creator","label":"Author","values":["Zhang, DongNi"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-02-10T16:54:58Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-02-10T16:54:58Z"]},{"key":"dc:date.issued","label":"Date","values":["2013"]},{"key":"dc:publisher","label":"Institution","values":["Massachusetts Institute of Technology"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrical Engineering and Computer Science."]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://dspace.mit.edu/handle/1721.1/7582"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1721.1/84855"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.","Cataloged from PDF version of thesis.","Includes bibliographical references (pages 83-84)."]},{"key":"dc:description.abstract","label":"Abstract","values":["The push for portable electronics for communication and biomedical applications has accelerated the growing momentum for high performance and low energy hardware implementations of the Fast Fourier Transform (FFT). This work presents several new hardware implementations of the radix-2 FFT algorithms that take advantage of intermittent data and parallelism to reduce the energy per FFT. In the modified serial design, by using a low-power control memory and a pipelined data look-ahead controller to optimize processing of sequences of data with zeros, up to 45% of energy savings are achieved as compared to the baseline design. Two fully parallel FFTs with different datapaths are also developed based on a FFT flow diagram with the same geometry in each stage. Energy savings of up to 90% (an order of magnitude) are achieved as compared to the baseline design. These results are demonstrated through post-layout and parasitic extraction Nanosim simulations with 90nm standard cell libraries."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["S.M."]},{"key":"dc:title","label":"Title","values":["Low-energy radix-2 serial and parallel FFT designs"]}]}],"canonical_facts":{"dc:contributor.advisor":["Anantha P. Chandrakasan."],"dc:contributor.department":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."],"dc:contributor.other":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."],"dc:creator":["Zhang, DongNi"],"dc:date.accessioned":["2014-02-10T16:54:58Z"],"dc:date.available":["2014-02-10T16:54:58Z"],"dc:date.issued":["2013"],"dc:description":["Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.","Cataloged from PDF version of thesis.","Includes bibliographical references (pages 83-84)."],"dc:description.abstract":["The push for portable electronics for communication and biomedical applications has accelerated the growing momentum for high performance and low energy hardware implementations of the Fast Fourier Transform (FFT). This work presents several new hardware implementations of the radix-2 FFT algorithms that take advantage of intermittent data and parallelism to reduce the energy per FFT. In the modified serial design, by using a low-power control memory and a pipelined data look-ahead controller to optimize processing of sequences of data with zeros, up to 45% of energy savings are achieved as compared to the baseline design. Two fully parallel FFTs with different datapaths are also developed based on a FFT flow diagram with the same geometry in each stage. Energy savings of up to 90% (an order of magnitude) are achieved as compared to the baseline design. These results are demonstrated through post-layout and parasitic extraction Nanosim simulations with 90nm standard cell libraries."],"dc:description.degree":["S.M."],"dc:identifier.uri":["http://hdl.handle.net/1721.1/84855"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Electrical Engineering and Computer Science."],"dc:title":["Low-energy radix-2 serial and parallel FFT designs"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:22:29Z"}