Wafer bonding of processed Si CMOS VLSI and GaAs for mixed technology integration

The successful bonding of bare thinned Si SOI wafers to bare GaAs wafers in previous research has proven to be an important first step in achieving integration of Si electronics with GaAs optoelectronic devices. The thinning of the SOI wafer has been shown to be a successful solution to the problem of the thermal expansion coefficient mismatch between Si and GaAs, allowing for the potential dense integration of mixed optoelectronic and electronic technologies. This research takes the next logical step toward that end by bonding Si wafers with simulated full back-end processing to GaAs wafers. The back-end processing simulation consists of depositing 1000[Angstroms] of Al, patterning the Al into 5[mu]m serpentine lines on a 5[mu]m pitch, covering the Al with a PECVD oxide, and performing CMP planarization of the oxide. The 1000[Angstroms] variations caused by the Al layer are consistent with surface profiles taken from fully processed SOI wafers obtained from IBM. The result is that these "simulation" wafers model the difficulties presented with bonding fully processed wafers; namely the temperature constraints caused by the existence of buried Al metal and the topography created by the patterned metal. The entire process, including the bonding and post-bond anneal, is carried out at temperatures below 45° C, making it compatible with a fully processed SOI CMOS wafer. The use of dielectric CMP has become a common back-end processing step. The wafer bonding in this work relies on CMP technology to planarize PECVD oxide deposited on the bonding surface of both wafers. The combination of CMP with post CMP cleaning methods results in a PECVD oxide surface with an order of magnitude reduction in the r.m.s. roughness, rendering the surface smooth enough to facilitate wafer bonding. The future goal of this project is to bond fully processed Si CMOS wafers to GaAs wafers containing optoelectronic devices and to test the feasibility of creating interconnects through the bond interface.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2002

Author dc:creator

• Barkley, Edward Robert, 1977-

Advisor dc:contributor.advisor

• Clifton G. Fonstad, Jr.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/8368

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/8368