{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/82394"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/82394","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"A compact transport and charge model for GaN-based high electron mobility transistors for RF applications","abstract":"Gallium Nitride (GaN)-based high electron mobility transistors (HEMTs) are rapidly emerging as front-runners in high-power mm-wave circuit applications. For circuit design with current devices and to allow sensible future performance projections from device engineering in such a rapidly evolving technology, compact device models are essential. In this thesis, a physics-based compact model is developed for short channel GaN HEMTs. The model is based on the concept of virtual source (VS) transport originally developed for scaled silicon field effect transistors. Self-consistent current and charge expressions in the model require very few parameters. The parameters have straightforward physical meanings and can be extracted through independent measurements. The model is implemented in Verilog-A and is compatible with state of the art circuit simulators. The new model is calibrated and validated with experimental DC I-V and S-parameter measurements of fabricated devices. Using the model, a projection of cut-off frequency (f-[tau]) of GaN-based HEMTs with scaling is performed to highlight performance bottlenecks.","abstract_html":"Gallium Nitride (GaN)-based high electron mobility transistors (HEMTs) are rapidly emerging as front-runners in high-power mm-wave circuit applications. For circuit design with current devices and to allow sensible future performance projections from device engineering in such a rapidly evolving technology, compact device models are essential. In this thesis, a physics-based compact model is developed for short channel GaN HEMTs. The model is based on the concept of virtual source (VS) transport originally developed for scaled silicon field effect transistors. Self-consistent current and charge expressions in the model require very few parameters. The parameters have straightforward physical meanings and can be extracted through independent measurements. The model is implemented in Verilog-A and is compatible with state of the art circuit simulators. The new model is calibrated and validated with experimental DC I-V and S-parameter measurements of fabricated devices. Using the model, a projection of cut-off frequency (f-[tau]) of GaN-based HEMTs with scaling is performed to highlight performance bottlenecks.","abstract_has_math":false,"creators":["Radhakrishna, Ujwal"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Dimitri A. Antoniadis."],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013","date_published":"2013","updated_at":"2026-07-22T22:21:52Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. 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For circuit design with current devices and to allow sensible future performance projections from device engineering in such a rapidly evolving technology, compact device models are essential. In this thesis, a physics-based compact model is developed for short channel GaN HEMTs. The model is based on the concept of virtual source (VS) transport originally developed for scaled silicon field effect transistors. Self-consistent current and charge expressions in the model require very few parameters. The parameters have straightforward physical meanings and can be extracted through independent measurements. The model is implemented in Verilog-A and is compatible with state of the art circuit simulators. The new model is calibrated and validated with experimental DC I-V and S-parameter measurements of fabricated devices. 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