{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/82389"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/82389","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Enhancement of antimonide-based p-channel quantum-well field effect transistors using process-induced sprain","abstract":"For decades, the scaling of silicon CMOS has brought impressive growth to the semiconductor industry, as well as a wealth of technological innovations. However, the continued scaling of CMOS devices to the nanometer regime is now threatened by intrinsic limitations to the use of silicon as the channel material. Hence, there is a strong interest in III-V semiconductor materials to replace silicon as the channel material as a result of their outstanding electron transport properties. While III-V materials have demonstrated impressive n-channel field-effect transistors (FETs), the same success has not yet been translated to the development of a high-performance III-V pchannel FET. This is because while many III-V's have high electron mobilities, they generally have very poor hole mobilities. The development of a high-performance III-V p-channel FET is critical to the realization of a future-generation III-V CMOS architecture. Among the III-Vs, the antimonides have the highest hole mobilities. This makes them attractive for developing a 111-V p-channel FET. This thesis examines the use of process-induced uniaxial strain combined with biaxial strain introduced during growth of the heterostructure as an approach to enhance antimonide-based FETs. Using a compressively stressed silicon nitride layer to induce uniaxial strain in the device, stressed devices with an InGaSb channel were fabricated and compared with unstressed devices processed in parallel. Enhancements of >50% in the intrinsic transconductance were observed as well as reductions of >30% in the source-drain resistance. This work illustrates the effectiveness of uniaxial strain in improving the performance of antimonide FETs.","abstract_html":"For decades, the scaling of silicon CMOS has brought impressive growth to the semiconductor industry, as well as a wealth of technological innovations. However, the continued scaling of CMOS devices to the nanometer regime is now threatened by intrinsic limitations to the use of silicon as the channel material. Hence, there is a strong interest in III-V semiconductor materials to replace silicon as the channel material as a result of their outstanding electron transport properties. While III-V materials have demonstrated impressive n-channel field-effect transistors (FETs), the same success has not yet been translated to the development of a high-performance III-V pchannel FET. This is because while many III-V's have high electron mobilities, they generally have very poor hole mobilities. The development of a high-performance III-V p-channel FET is critical to the realization of a future-generation III-V CMOS architecture. Among the III-Vs, the antimonides have the highest hole mobilities. This makes them attractive for developing a 111-V p-channel FET. This thesis examines the use of process-induced uniaxial strain combined with biaxial strain introduced during growth of the heterostructure as an approach to enhance antimonide-based FETs. Using a compressively stressed silicon nitride layer to induce uniaxial strain in the device, stressed devices with an InGaSb channel were fabricated and compared with unstressed devices processed in parallel. Enhancements of >50% in the intrinsic transconductance were observed as well as reductions of >30% in the source-drain resistance. This work illustrates the effectiveness of uniaxial strain in improving the performance of antimonide FETs.","abstract_has_math":false,"creators":["Guo, Luke (Luke W.)"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Jesús A. del Alamo."],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013","date_published":"2013","updated_at":"2026-07-22T22:20:54Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/82389","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Jesús A. del Alamo."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."]},{"key":"dc:contributor.other","label":"Dc Contributor Other","values":["Massachusetts Institute of Technology. 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However, the continued scaling of CMOS devices to the nanometer regime is now threatened by intrinsic limitations to the use of silicon as the channel material. Hence, there is a strong interest in III-V semiconductor materials to replace silicon as the channel material as a result of their outstanding electron transport properties. While III-V materials have demonstrated impressive n-channel field-effect transistors (FETs), the same success has not yet been translated to the development of a high-performance III-V pchannel FET. This is because while many III-V's have high electron mobilities, they generally have very poor hole mobilities. The development of a high-performance III-V p-channel FET is critical to the realization of a future-generation III-V CMOS architecture. Among the III-Vs, the antimonides have the highest hole mobilities. This makes them attractive for developing a 111-V p-channel FET. This thesis examines the use of process-induced uniaxial strain combined with biaxial strain introduced during growth of the heterostructure as an approach to enhance antimonide-based FETs. Using a compressively stressed silicon nitride layer to induce uniaxial strain in the device, stressed devices with an InGaSb channel were fabricated and compared with unstressed devices processed in parallel. Enhancements of >50% in the intrinsic transconductance were observed as well as reductions of >30% in the source-drain resistance. This work illustrates the effectiveness of uniaxial strain in improving the performance of antimonide FETs."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["S.M."]},{"key":"dc:title","label":"Title","values":["Enhancement of antimonide-based p-channel quantum-well field effect transistors using process-induced sprain"]}]}],"canonical_facts":{"dc:contributor.advisor":["Jesús A. del Alamo."],"dc:contributor.department":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."],"dc:contributor.other":["Massachusetts Institute of Technology. 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While III-V materials have demonstrated impressive n-channel field-effect transistors (FETs), the same success has not yet been translated to the development of a high-performance III-V pchannel FET. This is because while many III-V's have high electron mobilities, they generally have very poor hole mobilities. The development of a high-performance III-V p-channel FET is critical to the realization of a future-generation III-V CMOS architecture. Among the III-Vs, the antimonides have the highest hole mobilities. This makes them attractive for developing a 111-V p-channel FET. This thesis examines the use of process-induced uniaxial strain combined with biaxial strain introduced during growth of the heterostructure as an approach to enhance antimonide-based FETs. Using a compressively stressed silicon nitride layer to induce uniaxial strain in the device, stressed devices with an InGaSb channel were fabricated and compared with unstressed devices processed in parallel. Enhancements of >50% in the intrinsic transconductance were observed as well as reductions of >30% in the source-drain resistance. This work illustrates the effectiveness of uniaxial strain in improving the performance of antimonide FETs."],"dc:description.degree":["S.M."],"dc:identifier.uri":["http://hdl.handle.net/1721.1/82389"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Electrical Engineering and Computer Science."],"dc:title":["Enhancement of antimonide-based p-channel quantum-well field effect transistors using process-induced sprain"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:20:54Z"}