{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/68510"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/68510","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Front-end circuits for a photonic analog-to-digital converter","abstract":"As the resolution of electrical ADCs gets limited at higher sampling rates due to sampling clock jitter, low-jitter mode-lock laser based photonic ADCs are starting to gain more attention. As well as low-jitter and high-linearity operation at very high speeds, photonic ADCs provide the opportunity to de-multiplex electrical signals to enable the parallel sampling of signals which increases the total sampling speed dramatically. However, even in photonic systems, a careful optimization between the degree of de-multiplexing, the optical non-linearities and receiver front-end noise has to be performed to enable resolution and sampling rate gains to materialize. Electrical components still constitute the bottleneck for a photonic ADC system. Photo-detector front-end, which is responsible for the current-voltage transformation of the samples, is one of the most critical components for the overall linearity, noise and jitter performance of photonic ADC systems. This work focuses on photo-detector front-ends and investigates the performance of several structures as well as evaluating the performance of photonic ADC systems depending on the amount of photo-detector current. Integrator and trans-impedance amplifier flavors of the front-end circuits are designed, implemented, simulated and laid out for 6 ENOB and 10 ENOB linearity and noise performance at 1GS/s. The circuits are implemented on 45 nm SOI process and integrated with on-chip photonic components which allow on-chip and off-chip ADC implementations.","abstract_html":"As the resolution of electrical ADCs gets limited at higher sampling rates due to sampling clock jitter, low-jitter mode-lock laser based photonic ADCs are starting to gain more attention. As well as low-jitter and high-linearity operation at very high speeds, photonic ADCs provide the opportunity to de-multiplex electrical signals to enable the parallel sampling of signals which increases the total sampling speed dramatically. However, even in photonic systems, a careful optimization between the degree of de-multiplexing, the optical non-linearities and receiver front-end noise has to be performed to enable resolution and sampling rate gains to materialize. Electrical components still constitute the bottleneck for a photonic ADC system. Photo-detector front-end, which is responsible for the current-voltage transformation of the samples, is one of the most critical components for the overall linearity, noise and jitter performance of photonic ADC systems. This work focuses on photo-detector front-ends and investigates the performance of several structures as well as evaluating the performance of photonic ADC systems depending on the amount of photo-detector current. Integrator and trans-impedance amplifier flavors of the front-end circuits are designed, implemented, simulated and laid out for 6 ENOB and 10 ENOB linearity and noise performance at 1GS/s. The circuits are implemented on 45 nm SOI process and integrated with on-chip photonic components which allow on-chip and off-chip ADC implementations.","abstract_has_math":false,"creators":["Uyar, Oğuzhan"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Vladimir Stojanović."],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011","date_published":"2011","updated_at":"2026-07-22T22:22:26Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/68510","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Vladimir Stojanović."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."]},{"key":"dc:contributor.other","label":"Dc Contributor Other","values":["Massachusetts Institute of Technology. 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As well as low-jitter and high-linearity operation at very high speeds, photonic ADCs provide the opportunity to de-multiplex electrical signals to enable the parallel sampling of signals which increases the total sampling speed dramatically. However, even in photonic systems, a careful optimization between the degree of de-multiplexing, the optical non-linearities and receiver front-end noise has to be performed to enable resolution and sampling rate gains to materialize. Electrical components still constitute the bottleneck for a photonic ADC system. Photo-detector front-end, which is responsible for the current-voltage transformation of the samples, is one of the most critical components for the overall linearity, noise and jitter performance of photonic ADC systems. This work focuses on photo-detector front-ends and investigates the performance of several structures as well as evaluating the performance of photonic ADC systems depending on the amount of photo-detector current. Integrator and trans-impedance amplifier flavors of the front-end circuits are designed, implemented, simulated and laid out for 6 ENOB and 10 ENOB linearity and noise performance at 1GS/s. The circuits are implemented on 45 nm SOI process and integrated with on-chip photonic components which allow on-chip and off-chip ADC implementations."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["S.M."]},{"key":"dc:title","label":"Title","values":["Front-end circuits for a photonic analog-to-digital converter"]}]}],"canonical_facts":{"dc:contributor.advisor":["Vladimir Stojanović."],"dc:contributor.department":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."],"dc:contributor.other":["Massachusetts Institute of Technology. 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However, even in photonic systems, a careful optimization between the degree of de-multiplexing, the optical non-linearities and receiver front-end noise has to be performed to enable resolution and sampling rate gains to materialize. Electrical components still constitute the bottleneck for a photonic ADC system. Photo-detector front-end, which is responsible for the current-voltage transformation of the samples, is one of the most critical components for the overall linearity, noise and jitter performance of photonic ADC systems. This work focuses on photo-detector front-ends and investigates the performance of several structures as well as evaluating the performance of photonic ADC systems depending on the amount of photo-detector current. Integrator and trans-impedance amplifier flavors of the front-end circuits are designed, implemented, simulated and laid out for 6 ENOB and 10 ENOB linearity and noise performance at 1GS/s. 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