{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/63025"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/63025","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Current limiters based on silicon pillar un-gated FET for field emission application","abstract":"This research investigates the use of vertical silicon ungated field effect transistors (FETs) as current limiters to individuallycontrol emission current in a field emitter and provide a simple solution to three problems that have plagued field emission arrays-emission current uniformity, emission current stability and reliability. The ungated FET is an high aspect ratio silicon pillar individually connected in series with silicon or carbon nanofiber (CNF) emission tip. The transistors were designed as high aspect ratio silicon pillars in order to achieve velocity saturation of carriers and obtain current source-like characteristics. Device and process simulations were initially conducted to solidify the derived analytical model and optimize design parameters. Devices were fabricated and characterized in the Microsystems Technology Laboratory. The main outcome of this study is that individual control of field emitter current is feasible using un-gated FETs based vertical Si pillars.","abstract_html":"This research investigates the use of vertical silicon ungated field effect transistors (FETs) as current limiters to individuallycontrol emission current in a field emitter and provide a simple solution to three problems that have plagued field emission arrays-emission current uniformity, emission current stability and reliability. The ungated FET is an high aspect ratio silicon pillar individually connected in series with silicon or carbon nanofiber (CNF) emission tip. The transistors were designed as high aspect ratio silicon pillars in order to achieve velocity saturation of carriers and obtain current source-like characteristics. Device and process simulations were initially conducted to solidify the derived analytical model and optimize design parameters. Devices were fabricated and characterized in the Microsystems Technology Laboratory. The main outcome of this study is that individual control of field emitter current is feasible using un-gated FETs based vertical Si pillars.","abstract_has_math":false,"creators":["Niu, Ying, M. Eng. Massachusetts Institute of Technology"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Akintunde Ibitayo Akinwande."],"committee_chairs":[],"committee_members":[],"year":2009,"date_issued":"2009","date_published":"2009","updated_at":"2026-07-22T22:22:13Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/63025","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Akintunde Ibitayo Akinwande."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."]},{"key":"dc:contributor.other","label":"Dc Contributor Other","values":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."]},{"key":"dc:creator","label":"Author","values":["Niu, Ying, M. Eng. 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They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://dspace.mit.edu/handle/1721.1/7582"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1721.1/63025"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.","Cataloged from PDF version of thesis.","Includes bibliographical references (p. 56-58)."]},{"key":"dc:description.abstract","label":"Abstract","values":["This research investigates the use of vertical silicon ungated field effect transistors (FETs) as current limiters to individuallycontrol emission current in a field emitter and provide a simple solution to three problems that have plagued field emission arrays-emission current uniformity, emission current stability and reliability. The ungated FET is an high aspect ratio silicon pillar individually connected in series with silicon or carbon nanofiber (CNF) emission tip. The transistors were designed as high aspect ratio silicon pillars in order to achieve velocity saturation of carriers and obtain current source-like characteristics. Device and process simulations were initially conducted to solidify the derived analytical model and optimize design parameters. Devices were fabricated and characterized in the Microsystems Technology Laboratory. The main outcome of this study is that individual control of field emitter current is feasible using un-gated FETs based vertical Si pillars."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["M.Eng."]},{"key":"dc:title","label":"Title","values":["Current limiters based on silicon pillar un-gated FET for field emission application"]}]}],"canonical_facts":{"dc:contributor.advisor":["Akintunde Ibitayo Akinwande."],"dc:contributor.department":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."],"dc:contributor.other":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."],"dc:creator":["Niu, Ying, M. Eng. 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The transistors were designed as high aspect ratio silicon pillars in order to achieve velocity saturation of carriers and obtain current source-like characteristics. Device and process simulations were initially conducted to solidify the derived analytical model and optimize design parameters. Devices were fabricated and characterized in the Microsystems Technology Laboratory. The main outcome of this study is that individual control of field emitter current is feasible using un-gated FETs based vertical Si pillars."],"dc:description.degree":["M.Eng."],"dc:identifier.uri":["http://hdl.handle.net/1721.1/63025"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Electrical Engineering and Computer Science."],"dc:title":["Current limiters based on silicon pillar un-gated FET for field emission application"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:22:13Z"}