Massachusetts Institute of Technology
FastCaplet : an efficient 3D capacitance extraction solver using instantiable basis functions for VLSI interconnects
Abstract
dc:description.abstractState-of-the-art capacitance extraction methods for Integrated Circuits (IC) involve scanning 2D cross-sections, and interpolating 2D capacitance values using a table lookup approach. This approach is fast and accurate for a large percentage of IC wires. It is however quite inaccurate for full 3D structures, such as crossing wires in adjacent metal layers. For such cases electrostatic field solvers are required. Unfortunately standard field solvers are inherently very time-consuming, making them completely impractical in typical IC design flows. Even fast matrix-vector product approaches (e.g., fastmultipole or precorrected FFT) are inefficient for these structures since they have a significant computational overhead and scale linearly with the number of conductors only for much larger structures with more than several hundreds of wires. In this talk we present therefore a new 3D extraction field solver that is extremely efficient in particular for the smaller scale extraction problem involving the ten to one hundred conductors in the 3D structures that cannot be handled by the 2D scanning and table look up approach. Because of highly restrictive design rules of the recent sub-micro to nano-scale IC technologies, smooth and regular charge distributions extracted from simple model structures can be stored beforehand as "templates" and instantiated and stretched to fit practical complicated cases as basis function building blocks. This "template-instantiated" strategy largely reduces the number of unknowns and computational time without additional overhead. Given that all basis functions are obtained by the same very few stretched templates, Galerkin coefficients can be readily computed from a mixture of analytical, numerical and table lookup approaches. Furthermore, given the low accuracy (i.e., 3%-5%) required by IC extraction and the specific aspect ratios and separations of wires on ICs, we have observed in our numerical experimentations that edge and corner charge singularities do not need to be included in our templates, hence reducing the complexity of our solver even further.
Degree
thesis:*- Department dc:contributor.department
- Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
- Grantor dc:publisher
- Massachusetts Institute of Technology
- Year dc:date.issued
- 2010
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Hsiao, Yu-Chung, Ph. D. Massachusetts Institute of Technology
- Advisor dc:contributor.advisor
-
- Luca Daniel.
Subjects
dc:subject × 1Rights
dc:rights- Statement dc:rights
-
- M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
- Licence dc:rights.uri
- Language dc:language.iso
- eng
Identifiers
dc:identifier.*- Handle dc:identifier.uri
- http://hdl.handle.net/1721.1/62449
- OAI identifier oai:identifier
- oai:dspace.mit.edu:1721.1/62449