A 9GHz injection locked loop optical clock receiver in 32-nm CMOS

The bottleneck of multi-core processors performance will be the I/O, for both on-chip core-to-core I/0, and off-chip core-to-memory. Integrated silicon photonics can potentially provide high-bandwidth low-power signal and clock distribution for multicore processors, by exploiting wavelength-division multiplexing. This thesis presents the technology environment of the monolithic optical/electrical chip, and then focuses on how an optical method would look like for both source-synchronous link and for on-chip global clock distribution. The injection-locked loop clock receiver that suits this architecture breaks the bandwidth/sensitivity tradeoff, and a self-adjusting mechanism is added to increase robustness. The simulated receiver sensitivity is - 14dBm at 9GHz, consuming 77.14pW and generating jitter within 0. 15ps when locked onto a mode-locked laser clock source. The chip infrastructure and testing procedures are then presented, and lastly a truly integrated optical-electrical design flow is shown as well.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2010

Author dc:creator

• Leu, Jonathan Chung

Advisor dc:contributor.advisor

• Vladimir Stojanović.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/62443

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/62443