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Massachusetts Institute of Technology

Obtaining performance and programmability using reconfigurable hardware for media processing

Abstract

dc:description.abstract

An imperative requirement in the design of a reconfigurable computing system or in the development of a new application on such a system is performance gains. However, such developments suffer from long-and-difficult programming process, hard-to-predict performance gains, and limited scope of applications. To address these problems, we need to understand reconfigurable hardware's capabilities and limitations, its performance advantages and disadvantages, re-think reconfigurable system architectures, and develop new tools to explore its utility. We begin by examining performance contributors at the system level. We identify those from general-purpose and those from dedicated components. We propose an architecture by integrating reconfigurable hardware within the general-purpose framework. This is to avoid and minimize dedicated hardware and organization for programmability. We analyze reconfigurable logic architectures and their performance limitations. This analysis leads to a theory that reconfigurable logic can never be clocked faster than a fixed-logic design based on the same fabrication technology. Though highly unpredictable, we can obtain a quick upper bound estimate on the clock speed based on a few parameters. We also analyze microprocessor architectures and establish an analytical performance model. We use this model to estimate performance bounds using very little information on task properties. These bounds help us to detect potential memory-bound tasks. For a compute-bound task, we compare its performance upper bound with the upper bound on reconfigurable clock speed to further rule out unlikely speedup candidates.

Degree

thesis:*
Department dc:contributor.department
Massachusetts Institute of Technology. Dept. of Architecture. Program In Media Arts and Sciences.
Grantor dc:publisher
Massachusetts Institute of Technology
Year dc:date.issued
2002

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Kung, Ling-Pei, 1961-
Advisor dc:contributor.advisor
  • V. Michael Bove, Jr.

Subjects

dc:subject × 1

Rights

dc:rights
Statement dc:rights
  • M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
Language dc:language.iso
eng

Identifiers

dc:identifier.*
Handle dc:identifier.uri
http://hdl.handle.net/1721.1/61855
OAI identifier oai:identifier
oai:dspace.mit.edu:1721.1/61855

Chain of custody

source
Harvested from
MIT
Base URL
dspace.mit.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Kung, Ling-Pei, 1961-. Obtaining performance and programmability using reconfigurable hardware for media processing. Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/61855