{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/61581"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/61581","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Design and simulation of a PCI Express Gen 3.0 communication channel","abstract":"PCI Express (PCIe) is a serial interconnect technology, developed by the PCI-Sig organization, which provides high bandwidth data transmission with the added benefits of reduced board space requirements, smaller connectors and simplified PCB layouts. Since faster and faster data rates are more desirable, PCIe Gen 3.0 attempts to transmit data at 8GT/s. As part of the thesis work, an existing model of a PCIe channel which connects two controller boards over a backplane, was simulated and measured under PCIe Gen 2.0 speeds (5GT/s). The resulting data from these tests were used to provide the basis for improving the model to make it function under PCIe Gen 3.0 specifications. This was achieved by exploring new receiver equalization techniques and transmitter de-emphasis and board characteristics. An integrated circuit manufacturer's model was used as the base model for PCIe Gen 2.0. This model was further developed to simulate Gen 3.0 speeds. Simulation software tools such as HSPICE, Ansoft HFSS, Ansoft Via Wizard 3.0 and MATLAB were utilized. A simulation model of the system functioning under PCIe Gen 3.0 specifications was successfully developed by using CTLE equalization technique.","abstract_html":"PCI Express (PCIe) is a serial interconnect technology, developed by the PCI-Sig organization, which provides high bandwidth data transmission with the added benefits of reduced board space requirements, smaller connectors and simplified PCB layouts. Since faster and faster data rates are more desirable, PCIe Gen 3.0 attempts to transmit data at 8GT/s. As part of the thesis work, an existing model of a PCIe channel which connects two controller boards over a backplane, was simulated and measured under PCIe Gen 2.0 speeds (5GT/s). The resulting data from these tests were used to provide the basis for improving the model to make it function under PCIe Gen 3.0 specifications. This was achieved by exploring new receiver equalization techniques and transmitter de-emphasis and board characteristics. An integrated circuit manufacturer's model was used as the base model for PCIe Gen 2.0. This model was further developed to simulate Gen 3.0 speeds. Simulation software tools such as HSPICE, Ansoft HFSS, Ansoft Via Wizard 3.0 and MATLAB were utilized. A simulation model of the system functioning under PCIe Gen 3.0 specifications was successfully developed by using CTLE equalization technique.","abstract_has_math":false,"creators":["Warnakulasuriyarachchi, Dilini (Dilini M.)"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Scott Westbrook and Vladimir Stojanovic."],"committee_chairs":[],"committee_members":[],"year":2010,"date_issued":"2010","date_published":"2010","updated_at":"2026-07-22T22:21:52Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. 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This was achieved by exploring new receiver equalization techniques and transmitter de-emphasis and board characteristics. An integrated circuit manufacturer's model was used as the base model for PCIe Gen 2.0. This model was further developed to simulate Gen 3.0 speeds. Simulation software tools such as HSPICE, Ansoft HFSS, Ansoft Via Wizard 3.0 and MATLAB were utilized. A simulation model of the system functioning under PCIe Gen 3.0 specifications was successfully developed by using CTLE equalization technique."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["M.Eng."]},{"key":"dc:title","label":"Title","values":["Design and simulation of a PCI Express Gen 3.0 communication channel"]}]}],"canonical_facts":{"dc:contributor.advisor":["Scott Westbrook and Vladimir Stojanovic."],"dc:contributor.department":["Massachusetts Institute of Technology. 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