{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/61576"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/61576","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Concurrent gate-level circuit simulation","abstract":"In the last several years, parallel computing on multicore processors has transformed from a niche discipline relegated primarily to scientific computing into a standard component of highperformance personal computers. At the same time, simulating processors prior to manufacture has become increasingly time-consuming due to the increasing number of gates on a single chip. However, writing parallel programs in a way that significantly improves performance can be a difficult task. In this thesis, I outline principles that must be considered when running good gate-level circuit simulations in parallel. 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