Cache coherence strategies in a many-core processor

Caches are frequently employed in memory systems, exploiting memory locality to gain advantages in high-speed performance and low latency. However, as computer processor core counts increase, maintaining coherence between caches becomes increasingly difficult. Current methods of cache coherence work well in small-scale multi-core processors, however, the viability of cache coherence as processors scale to thousands of cores remains an open question. A novel many-core execution-driven performance simulator, called Graphite and implemented by the Carbon group, has been utilized to study a variety of cache coherency strategies of processors up to 256 cores. Results suggest that cache coherence may be possible in future many-core processors, but that software developers will have to exercise great care to match their algorithms to the target architecture to avoid sub-optimal performance.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2009

Author dc:creator

• Celio, Christopher P

Advisor dc:contributor.advisor

• Anant Agarwal.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/61276

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/61276