Fabrication of high aspect ratio silicon nanostructure arrays by metal-assisted etching

The goal of this research was to explore and understand the mechanisms involved in the fabrication of silicon nanostructures using metal-assisted etching. We developed a method utilizing metal-assisted etching in conjunction with block copolymer lithography to create ordered and densely-packed arrays of high-aspect-ratio single-crystal silicon nanowires with uniform crystallographic orientations. Nanowires with sub-20 nm diameters were created as either continuous carpets or as carpets within trenches. Wires with aspect ratios up to 220 with much reduced capillary-induced clustering were achieved through post-etching critical point drying. The size distribution of the diameters was narrow and closely followed the size distribution of the block copolymer. Fabrication of wires in topographic features demonstrated the ability to accurately control wire placement. The flexibility of this method will facilitate the use of such wire arrays in micro- and nano-systems in which high device densities and/or high surface areas are desired. In addition, we report a systematic study of metal-catalyzed etching of (100), (110), and (111) silicon substrates using gold catalysts with varying geometrical characteristics. It is shown that for isolated catalyst nanoparticles and metal meshes with small hole spacings, etching proceeded preferentially in the <100> direction. However, etching was confined in the direction vertical to the substrate surface when a catalyst mesh with large hole spacings was used. This result was used to demonstrate the use of metal-assisted etching to create arrays of vertically-aligned polycrystalline and amorphous silicon nanowires etched from deposited silicon thin films using catalyst meshes with relatively large hole spacings. The ability to pattern wires from polycrystalline and amorphous silicon thin films opens the possibility of making silicon nanowire-array-based devices on a much wider range of substrates. Finally, we demonstrated the fabrication of a silicon-nanopillar-based nanocapacitor array using metal-assisted etching and electrodeposition. The capacitance density was increased significantly as a result of an increased electrode area made possible by the catalytic etching approach. We also showed that the measured capacitance densities closely follow the expected trend as a function of pillar height and array period. The capacitance densities can be further enhanced by increasing the array density and wire length with the incorporation of known self-assembly-based patterning techniques such as block copolymer lithography.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Materials Science and Engineering.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2010

Author dc:creator

• Chang, Shih-wei, Ph.D. Massachusetts Institute of Technology

Advisor dc:contributor.advisor

• Carl V. Thompson.

• Materials Science and Engineering.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/59214

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/59214