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Massachusetts Institute of Technology

Quantum capacitance in scaled down III-V FETs

Abstract

dc:description.abstract

As Si CMOS approaches the end of the roadmap, finding a new transistor technology that allows the extension of Moore's law has become a technical problem of great significance. Among the various candidates, III-V-based MOSFETs represent a very promising technology. In particular, low-effective mass materials with high electron velocities, such as InGaAs and InAs are of great interest. A concern with this approach is the relatively small inversion-layer capacitance that is associated with a low-effective mass channel and the limits that this imposes on the gate capacitance that can be attained from barrier thickness scaling. This can seriously limit the current driving ability of scaled down devices. In order to understand the scaling potential of III-V MOSFETs, we have built a physical gate capacitance model for III-V FETs that incorporates quantum capacitance and centroid capacitance in the channel. We verified its validity with simulations (Nextnano) and experimental measurements on High Electron Mobility Transistors (HEMTs) with InAs and InGaAs channels down to 30 nm in gate length. Our model confirms that in the operational range of these devices, the quantum capacitance significantly lowers the overall gate capacitance. In addition, our experiments suggest a large increase of the in-plane effective mass in very thin channel designs as a result of non-parabolicity, quantum confinement and biaxial compressive strain. This should help to achieve a relatively high electron concentration in future 10 nm high-k dielectric Ill-V MOSFETs. Our study provides a number of suggestions for capacitance scaling in future Ill-V MOSFETs.

Degree

thesis:*
Department dc:contributor.department
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Grantor dc:publisher
Massachusetts Institute of Technology
Year dc:date.issued
2010

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Jin, Donghyun
Advisor dc:contributor.advisor
  • Jesús A. del Alamo.

Subjects

dc:subject × 1

Rights

dc:rights
Statement dc:rights
  • M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
Language dc:language.iso
eng

Identifiers

dc:identifier.*
Handle dc:identifier.uri
http://hdl.handle.net/1721.1/58178
OAI identifier oai:identifier
oai:dspace.mit.edu:1721.1/58178

Chain of custody

source
Harvested from
MIT
Base URL
dspace.mit.edu/oai/request
Last updated
2026-07-22
Source record
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citation

Jin, Donghyun. Quantum capacitance in scaled down III-V FETs. Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/58178