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Massachusetts Institute of Technology

Effective modeling of throughput time in semiconductor assembly processes

Abstract

dc:description.abstract

We develop discrete event simulation (DES) models of a semiconductor assembly process capable of predicting average throughput time (TPT) within 6% of factory-floor measured average TPT. This represents a significant improvement over current DES models in the semiconductor industry, which commonly yield average TPTs that are 25% to 50% less than those measured on the factory floor. We accomplish this improvement by (1) constructing a separate area model of the system's constraint, (2) inputting an exact lot-starts schedule to the model, and (3) using failure parameters which are operation dependent rather than time dependent. In addition, we devise heuristics to parallelize the simulation process and significantly reduce computational expense in DES models, thereby affording the inclusion of detailed factors. We perform various sensitivity studies on the assembly's constraining process which indicate that operators and shift effects do not have a significant effect on average TPT. We also apply the series-parallel flow-line analytical model developed by Gershwin [8] and Burman [2], obtaining average TPTs which are 27% of factory-floor measured average TPT with numerical computational times of under a second.

Degree

thesis:*
Department dc:contributor.department
Massachusetts Institute of Technology. Department of Mechanical Engineering
Grantor dc:publisher
Massachusetts Institute of Technology
Year dc:date.issued
1998

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Cervantes José A. (José Armando), 1973-
Advisor dc:contributor.advisor
  • Kevin Otto and Stanley B. Gershwin.

Subjects

dc:subject × 2

Rights

dc:rights
Statement dc:rights
  • M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
Language dc:language.iso
eng

Identifiers

dc:identifier.*
Handle dc:identifier.uri
http://hdl.handle.net/1721.1/50485
OAI identifier oai:identifier
oai:dspace.mit.edu:1721.1/50485

Chain of custody

source
Harvested from
MIT
Base URL
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Last updated
2026-07-22
Source record
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citation

Cervantes José A. (José Armando), 1973-. Effective modeling of throughput time in semiconductor assembly processes. Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/50485