A 4th order continuous-time [Delta] [Epsilon] ADC with VCO-based integrator and quantizer

The use of a VCO-based integrator and quantizer within a continuous-time (CT) [Delta] [Epsilon] analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 [mu]m CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1.5V supply and occupying an active area of 0.45 mm2 demonstrated. A key innovation is the explicit use of the oscillator's output phase to avoid the signal distortion that had severely limited the performance of earlier VCO-based ADC's, which exclusively made use of the output frequency. Furthermore, the proposed architecture includes a scheme for performing fast dynamic element matching (DEM), enabling first-order shaping of unit-element mismatch in all feedback DAC's.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2009

Author dc:creator

• Park, Matthew Jeremiah

Advisor dc:contributor.advisor

• Michael H. Perrott.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/47755

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/47755