A high performance zero-crossing based pipelined analog-to-digital converter

In this thesis, I describe a zero-crossing based pipelined ADC. Unlike traditional pipelined ADCs, this work does not use any op-amps in the signal path. The use of zero-crossing based circuits made it possible to achieve a much better figure of merit. The ADC is design to operate at 200MS/s with a resolution of 12 bits. The simulated results suggest that the target performance is achievable with less than 10 mW of power. This design's figure of merit is at least an order of magnitude better than any existing designs that have comparable speed and accuracy performance. The design will be fabricated later to be tested in silicon.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2008

Author dc:creator

• Chu, Yue Jack

Advisor dc:contributor.advisor

• Hae-Seung Lee.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/44377

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/44377