Channel coding for high speed links

This thesis explores the benefit of channel coding for high-speed backplane or chip-to-chip interconnects, referred to as the high-speed links. Although both power-constrained and bandwidth-limited, the high-speed links need to support data rates in the Gbps range at low error probabilities. Modeling the high-speed link as a communication system with noise and intersymbol interference (ISI), this work identifies three operating regimes based on the underlying dominant error mechanisms. The resulting framework is used to identify the conditions under which standard error control codes perform optimally, incur an impractically large overhead, or provide the optimal performance in the form of a single parity check code. For the regime where the standard error control codes are impractical, this thesis introduces low-complexity block codes, termed pattern-eliminating codes (PEC), which achieve a potentially large performance improvement over channels with residual ISI. The codes are systematic, require no decoding and allow for simple encoding. They can also be additionally endowed with a (0, n - 1) run-length-limiting property. The simulation results show that the simplest PEC can provide error-rate reductions of several orders of magnitude, even with rate penalty taken into account. It is also shown that channel conditioning, such as equalization, can have a large effect on the code performance and potentially large gains can be derived from optimizing the equalizer jointly with a pattern-eliminating code. Although the performance of a pattern-eliminating code is given by a closed-form expression, the channel memory and the low error rates of interest render accurate simulation of standard error-correcting codes impractical. This work proposes performance estimation techniques for coded high-speed links, based on the underlying regimes of operation.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2008

Author dc:creator

• Blitvic, Natasa

Advisor dc:contributor.advisor

• Vladimir Stojanovic.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/43050

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/43050